View C5NPD0-DS_240170.PDF datasheet online --- IC-ON-LINE

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Data Sheet
C-5 NETWORK PROCESSOR SILICON REVISION D0
Freescale Semiconductor, Inc...
C5NPD0-DS/D Rev 04
Freescale Semiconductor, Inc...
Data Sheet
Freescale Semiconductor, Inc...
C-5 Network Processor Silicon Revision D0
C5NPD0-DS/D Rev 04
Freescale Semiconductor, Inc...
C5NPD0-DS/D Rev 04
CONTENTS
Freescale Semiconductor, Inc...
About This Guide
Data Sheet Description and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using C-Port Electronic Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Guide Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 14 15 17
CHAPTER 1
Functional Description
Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Executive Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fabric Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table Lookup Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Queue Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 21 22 22 23 24 24 25 25 25
CHAPTER 2
Signal Descriptions
Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions Grouped by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVTTL and LVPECL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CP Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS1/T1 Framer Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/100 Ethernet (RMII) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gigabit Ethernet (GMII) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gigabit Ethernet and Fibre Channel TBI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SONET OC-3 Transceiver Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 28 29 29 30 32 32 33 35 37
V 04
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CONTENTS
Freescale Semiconductor, Inc...
SONET OC-12 Transceiver Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Executive Processor System Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General System Interface Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fabric Processor Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BMU SDRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLU SRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QMU SRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No Connection Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signals Grouped by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Cell Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDcode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Description Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37 39 39 40 41 43 44 47 49 50 50 52 53 53 63 63 63 63 64 65 66
CHAPTER 3
Electrical Specifications
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CP Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS1/DS3 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/100 Ethernet Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gigabit GMII Ethernet, TBI and MII Interface Timing Specifications . . . . . . . . . . . . . . . . . . OC-3 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OC-12 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Executive Processor Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 67 68 69 70 72 73 75 75 76 77 79 81 82
C5NP
CONTENTS
7
Freescale Semiconductor, Inc...
PCI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO Serial Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Speed Serial Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROM Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fabric Processor Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BMU Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLU Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QMU Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82 83 84 85 86 88 90 91
CHAPTER 4
Mechanical Specifications
Package Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Marking Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Reflow Profile for the C-5 Switch Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 94 95 95 95
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
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8
CONTENTS
C5NP
C5NPD0-DS/D Rev 04
List of Figures
Freescale Semiconductor, Inc...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
C-5 Network Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GMII/TBI Transmit and Receive Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROM Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROM Interface Timing Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power and Ground Connections (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Observe-Only Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cell Design That Can Be Used for Both Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . Bringup Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Performance for C-5 Network Processor Heat Sink (see step 2 above). . . . . . . . . . Test Loading Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS1/DS3 Ethernet Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/100 Ethernet Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gigabit Ethernet and TBI Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OC-3 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OC-12 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO Serial Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Speed Serial Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROM Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fabric Processor Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BMU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QMU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5 Network Processor BGA Package Side View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5 Network Processor BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21 28 34 42 43 52 64 64 70 72 73 74 76 77 78 80 81 82 84 85 86 87 89 90 91 93 94
V 04
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C5NPD0-DS/D Rev 04
List of Tables
Freescale Semiconductor, Inc...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Navigating Within a C-Port Electronic Document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5 Network Processor Data Sheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-Port Silicon Documentation Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLU SRAM Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock and Reference Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CP Physical Interface Signals and Pins (Grouped by Clusters) . . . . . . . . . . . . . . . . . . . . . . . DS1/T1 Framer Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/100 Ethernet Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit and Receive Pin Combinations for Gigabit Ethernet and Fibre Channel . . . . . . . . . Gigabit Ethernet (GMII/MII) Signals One Cluster Example. . . . . . . . . . . . . . . . . . . . . . . . . . . Gigabit Ethernet and Fibre Channel TBI Signals Example . . . . . . . . . . . . . . . . . . . . . . . . . . OC-3 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OC-12 Signals Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General System Interface Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fabric Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Utopia1*, 2, 3 ATM Mode, C-5 Network Processor to Fabric Interface Pin Mapping . . . . . Utopia1*, 2, 3 PHY Mode, C-5 Network Processor to Fabric Interface Pin Mapping . . . . . . PRIZMA Mode, C-5 Network Processor to Fabric Interface Pin Mapping . . . . . . . . . . . . . . . Power X Mode, C-5 Network Processor to Fabric Interface Pin Mapping . . . . . . . . . . . . . . . BMU SDRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLU SRAM Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QMU SRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines . . . . . . . . . . . . . No Connection Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 14 15 18 25 29 31 32 32 33 34 36 37 38 39 41 41 44 44 45 45 46 47 47 49 49 50 50 53 53
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Freescale Semiconductor, Inc...
30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58
Signals Listed by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Internal Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Identification Code and Its Sub-components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Register Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5 Network Processor Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5 Network Processor Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . C-5 Network Processor DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5 Network Processor Capacitance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5 Network Processor Power and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . System Clock Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS1/DS3 Ethernet Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/100 Ethernet Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gigabit GMII/MII Ethernet Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Gigabit TBI Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OC-3 Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OC-12 Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO Serial Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Speed Serial Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROM Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fabric Processor Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BMU Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Groups in BMU Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLU Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Groups in TLU Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QMU Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Groups in QMU Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Measurements (Reference Figure 26 and Figure 27 for Symbols) . . . . . . . . . . . . . C-5 Network Processor Marking Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54 63 65 65 67 68 68 69 70 74 76 77 79 79 80 81 83 84 85 86 87 89 89 90 90 91 92 95 95
C5NP
C5NPD0-DS/D Rev 04
ABOUT THIS GUIDE
Freescale Semiconductor, Inc...
Data Sheet Description and Organization
This data sheet describes the C-5 Network processor, Version D0. It provides hardware layout specifications including pinouts, memory configuration guidelines, timing diagrams, power and power sequencing guidelines, thermal design guidelines, and mechanical specifications. The data sheet is divided into the following topics:
* * * *
Using C-Port Electronic Documents
Functional Description Signal Descriptions Electrical Specifications Mechanical Specifications
C-Port electronic documents are provided as PDF files. Open and view them using the Adobe(R) Acrobat(R) Reader application, verion 3.0 or later. If necessary, download the Acrobat Reader from the Adobe Systems, Inc. web site: http://www.adobe.com/prodindex/acrobat/readstep.html Each provided PDF file offers several ways for moving among the document's pages, as follows: To move quickly from section to section within the document, use the Acrobat bookmarks that appear on the left side of the Acrobat Reader window. The bookmarks provide an expandable `outline' view of the document's contents. To display the document's Acrobat bookmarks, press the `Display both bookmarks and page' button on the Acrobat Reader tool bar. To move to the referenced page of an entry in the document's Contents or Index, click on the entry itself, each of which is "hot linked." To follow a cross-reference to a heading, figure, or table, click the blue text.
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To move to the beginning or end of the document, to move page by page within the document, or to navigate among the pages you displayed by clicking on hyperlinks, use the Acrobat Reader navigation buttons shown in this figure:
Beginning of document End of document Previous or next hyperlink Previous page Next page
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Table 1 summarizes how to navigate within a C-Port electronic document.
Table 1 Navigating Within a C-Port Electronic Document
TO NAVIGATE THIS WAY CLICK THIS
Move from section to section within the document.
A bookmark on the left side of the Acrobat Reader window
Move to an entry in the document's Contents The entry itself or Index. Follow a cross-reference (highlighted in blue The cross-reference text text). Move page by page. Move to the beginning or end of the document. The appropriate Acrobat Reader navigation buttons The appropriate Acrobat Reader navigation buttons
Move backward or forward among a series of The appropriate Acrobat Reader navigation hyperlinks you have selected. buttons
Guide Conventions
The following visual elements are used throughout this guide, where applicable: This icon and text designates information of special note.
Warning: This icon and text indicate a potentially dangerous procedure. Instructions contained in the warnings must be followed.
C5NP
Revision History
15
Warning: This icon and text indicate a procedure where the reader must take precautions regarding laser light.
This icon and text indicate the possibility of electro-static discharge (ESD) in a procedure that requires the reader to take the proper ESD precautions.
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Revision History
Table 2 shows the revision history for this data sheet, providing a description of the changes.
Table 2 C-5 Network Processor Data Sheet Revision History
REVISION DATE CHANGE PAGE NO.
March 10, 2000 June 12, 2000
First printing for the C-5 NP. Chapter 2 contains the following revisions:
* LVTTL and LVPECL specifications have been added. * Several of the tables listing pin configurations have had
their descriptions updated. Check each application's configuration table as required. * CPn3+1 is RCLKN (5/25/00), not NC (3/10/00) * Mechanism for EPROM signaling has changed. * XPUHOT functionality is clarified * QCPA is a NC (5/25/00), not Address Parity (3/10/00) * The power and ground connections illustration has been updated. Chapter 3 contains the following revisions: * Many values listed in individual timing diagrams and specification tables have updated or corrected. Check each specification table as required. * Low speed serial interface timing specifications have been added. * PROM I/F timing specifications are changed June 14, 2000 July 17, 2000 QMU timing specification for Tqdo has been changed from 2.2 to 1.5. Updated BMU section to reflect change to external Pipeline Architecture, Single Data Rate Synchronous DRAM.
17 18 - 39 25 31 31 36 38
61 - 78 71 72
77 12
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Table 2 C-5 Network Processor Data Sheet Revision History
REVISION DATE CHANGE PAGE NO.
August 8, 2000
Freescale Semiconductor, Inc...
Operating temperatiure range added. Power sequencing diagram updated. BMU timing diagram updated. TLU timing diagram updated. QMU timing diagram updated. Chapter 1 contains the following revisions: * Fabric Processor Interface Frequency changed from 100 MHz to 110 MHz thruoughout. * TLU interface memory was incorrectly noted at 64 MBytes. Changed to 32 MBytes. The maximum amount of memory supported by the TLU is 32MBytes in four banks. Chapter 2 contains the following revisions: * Buffer Management Unit (BMU) has 161 pins * Added Figure 5. PROM Interface Timing Outline * Added Figure 7. Observe-Only Cell * Added Figure 8. Cell Design That Can Be Used for Both Input and Output Pins * PROM Interface Timing Outline added. * Numerous changes in tables 17, 18 and 19 * Data lines incorrectly noted at 128. The useful configuration is 139 data lines and all 12 address lines. * The TLU SRAM interface was incorrectly noted at 64 MBytes. Changed to 32 MBytes. Chapter 3 contains the following revisions: * Table 40, Gigabit Ethernet (TBI) Timing Description, Tcgr min value of -1.0 removed. * Figure 16, OC 12 Clock Duty Cycle was added * Tc12d added to Table 42 * Figure 17, Executive Processor PCI Timing Diagram PGNTX is only an input. PGNTX Output removed. * Tpgo, Tpgz, Tpgv removed from Table 43. Chapter 4 contains the following revisions: * Mechanical specs changed.
54 56 75 77 78 Thru-out
March 26, 2001
18
19
21 37 57
36 39, 40 41 42
71 73 73 74 75
C5NP
Related Product Documentation
17
Table 2 C-5 Network Processor Data Sheet Revision History
REVISION DATE CHANGE PAGE NO.
October 1, 2001
Freescale Semiconductor, Inc...
Chapter 2 contains the following revisions: * LVTTL and LVPECL conform to the JEDEC JESD8-BSpecification * Table 3 changed to note LVPECL differential signal * Table 10 LVPECL change * Table 11 CPn_6 and CPn+1_6 changed * Table 21 changed to reflect pin G14 used for signal MDQML * Table 27 changed to reflect total number of NC pins for D0 * Table 28 changed to reflect G14 receiving signal MDQML * C-Port web site support address added Chapter 3 contains the following revisions * Table 32 Storage / max junction temperatures added * Table 34 LVPECL high and low voltage min / max added * Table 36 Power dissipation, PD min, max, typical changed Chapter 4 contains the following revisions * Added "Marking Codes" * Added "Reflow" profile
23 23 31 31 32 42 48 61 63 65 67 91 91
September 9, 2002 Chapter 1 contains the following revisions: * Table 4 contain revised TLU SRAM Configuration 25 specifications Chapter 2 contains the following revisions: * TLU SRAM Interface Signals: Table 24 and Table 25 changed 49 to reflect Memory Bank Selection Chapter 3 contains the following revisions: * Table 50, Table 51 and Table 53 contain revised timing 87 thru 90 specifications
Related Product Documentation
The following table lists the C-5 and CST documentation set. Find the latest editions of these documents for your installed CST version in the Support section of the C-Port Corporation web site:
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Table 3 C-Port Silicon Documentation Set
DOCUMENT SUBJECT DOCUMENT NAME PURPOSE DOCUMENT ID
Processor Information
C-5 Network Processor Architecture Guide
Describes the full architecture of the C-5 network processor.
C5NPARCH-RM/D
Freescale Semiconductor, Inc...
C5NP
C5NPD0-DS/D
Chapter 1
Rev 04
FUNCTIONAL DESCRIPTION
Freescale Semiconductor, Inc...
Feature List
Complete programmability
* *
Programmability at all levels of the protocol stack: Layers 2-7 Examples of C-5 enabled systems: - Multiservice Access Platforms (MSAPs) - Optical edge switch/routers - IP Gigabit/Terabit routers - WAN Customer Premises Equipment (CPE) - Load balancing web server switches
Simple programming model
* * * *
C/C++ programmable Standard instruction set Standard Applications Programming Interface (C-Ware APITM) Comprehensive C-WareTM Software Toolset (easy to program, debug, and tune applications)
Maximum system flexibility
* * * * *
Software implementation of functions from physical interfaces through switching fabric support Reprogram to support new functionality and ratified standards, improving your time-in-marketTM metric Deliver new services to market through simple software upgrades -- no forklift
Massive processing power
Operating frequencies: 166MHz, 200MHz, and 233MHz 5Gbps of bandwidth (for non-blocking throughput)
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CHAPTER 1: FUNCTIONAL DESCRIPTION
* * * * * * * *
More than 3,000MIPs of computing power (for adding services throughout the protocol stack) Up to 15 million packets per second transmitted at wire speed 17 programmable RISC Cores (for cell/packet forwarding) 32 programmable Serial Data Processors (for processing bit streams) Up to 133 million table lookups per second Three internal buses for 60Gb of aggregate bandwidth
Freescale Semiconductor, Inc...
High functional integration
838 pin Ball Grid Array (BGA) package 16 Channel Processors including: - Embedded OC-3c, OC-12, OC-12c SONET framers - Programmable MAC interface - RISC Cores - Programmable pin PHY interfaces Embedded coprocessors for table lookup (classification), buffer memory (payload control), and queue management (CoS/QoS implementation) Dedicated Fabric Processor and port Embedded RISC Executive Processor Integrated 32bit/66MHz PCI bus
* * * * * * * *
Stable programming interfaces
Supports generic communications programming interfaces to simplify programming and allow future reuse of code across generations of the processor Network Processing Forum (NPF), (formerly CPIX), Charter member
Third-party support
Support for virtually any third-party protocol stack, PHY or fabric interface, and industry standard tools Smart Networks Alliance Program ensures a wide range of verified solutions
C5NP
Block Diagram
21
Block Diagram
The C-5TM network processor, has an architecture specifically designed for networking applications. Figure 1 shows a block diagram of the C-5 NP, including its potential external interfaces. The following sections describe each component of the C-5 NP. For more information about the architecture of the C-5 NP, see the C-5 Network Processor Architecture Guide.
Freescale Semiconductor, Inc...
Figure 1 C-5 Network Processor Block Diagram
SRAM SRAM
Fabric
External Host CPU (optional)
External PROM (optional)
SDRAM
Control Logic (optional)
Table Lookup Unit
PCI Serial PROM
Fabric Processor
Executive Processor
Queue Mgmt Unit
Buses (60Gbps Bandwidth)
Buffer Mgmt Unit
C-5 NP
CP-0 CP-1 CP-2 CP-3
Cluster
PHY
PHY
PHY
CP-12 CP-13 CP-14 CP-15
Cluster
Channel Processors
Processor Boundary
PHY
PHY
PHY
PHY
PHY
PHY Interface Examples: 10/100 Ethernet Gigabit Ethernet OC-3 OC-12
The main components of the C-5 NP are:
* * * * * *
Channel Processors Executive Processor Fabric Processor Buffer Management Unit Table Lookup Unit Queue Management Unit
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CHAPTER 1: FUNCTIONAL DESCRIPTION
Channel Processors
Freescale Semiconductor, Inc...
The C-5 NP contains sixteen programmable Channel Processors (CPs) that receive, process, and transmit network data. The number of CPs per port is configurable, depending on the line interface. Typically one CP is assigned to each port for medium bandwidth applications (Fast Ethernet to OC-3). Multiple CPs can be assigned to a port in a configuration called channel aggregation in high bandwidth applications (greater than OC-3). Multiple logical ports can be assigned to a single CP, with the addition of an external multiplexor, for low bandwidth applications, such as DS1 to DS3. The C-5 NP's architecture supports a variety of industry-standard serial and parallel protocols and individual port data rates including:
* * * * * *
10Mb Ethernet (RMII) 100Mb Ethernet (RMII) 1Gb Ethernet (GMII and TBI) OC-3 OC-12 DS1/DS3, supported through the use of external framers/multiplexors
The C-5 NP's programmability can also support a variety of special interfaces, such as various xDSL encapsulations and proprietary protocols. Key components of each CP are a RISC Core (CPRC) that orchestrates cell/packet processing and a set of microprogrammable, special-purpose processors, called Serial Data Processors (SDPs), that provide features such as Ethernet MAC and SONET framing, multichannel HDLC, and ATM cell delineation. This means you usually only need to include PHYs to complete the system.
Executive Processor
The Executive Processor (XP) serves as a centralized computing resource for the C-5 NP and manages the system interfaces. The XP performs conventional supervisory tasks in the C-5 NP, including:
* * *
Reset and initialization of the C-5 NP Program loading and control of CPs Centralized exception handling
C5NP
Fabric Processor
23
* *
System Interfaces
Management of a host interface through the PCI Management of system interfaces (PCI, Serial Bus, PROM)
The system interfaces to the XP are:
*
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PCI -- Provides an industry standard 32bit 33/66MHz PCI channel used for chip-level shared resources. The PCI has both initiator and target capabilities. The PCI interface is typically connected to a host processor. Serial Bus Interface -- Provides a general purpose bi-directional, two-wire serial bus and I/O port that allows the C-5 NP to control external logic with either of two standard protocols: - The MDIO (high-speed) protocol: uses a 16bit data format with 10bits of addressing and supports transfers up to 25MHz. - The low-speed protocol: uses an 8bit data format followed by an acknowledge bit and supports transfers up to 400kbps. Software is used to select which protocol to use, by setting the appropriate bits in the Serial Bus Configuration Register. When a serial bus transfer is active, an external pin is driven by the C-5 NP to indicate which protocol is being used (SPLD=0 indicates MDIO protocol; SPLD=1 indicates low-speed protocol). Both SIDA and SICL are bi-directional lines that are connected, via an external pull-up resistor, to a positive supply voltage. When the bus is free, both lines are HIGH because of the pull-up resistor. The output stages of the devices connected to the bus must have either an open-drain or open-collector in order to perform the wired-AND function required for its arbitration mechanism.
*
*
PROM Interface -- Allows the XP to boot from nonvolatile, flash memory. The PROM interface is a low-speed, serial I/O port that runs at 1/2 to 1/16 the core clock rate. The maximum PROM size is 8MBytes, and a 16bit wide configuration is required. External board logic is required to perform serial-to-parallel conversion for PROM address outputs and parallel-to-serial conversion for PROM data inputs.
Fabric Processor
The Fabric Processor (FP) acts as a high-speed network interface port with advanced functionality. It allows the C-5 NP to interface to an application-specific switching solution internal to your design. The FP port supports the bidirectional transfer of packets, frames,
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CHAPTER 1: FUNCTIONAL DESCRIPTION
or cells from the C-5 NP to a hardware interface that provides connectivity to other network processors or other similar line processing hardware. There are numerous parameters that can be configured within the FP to allow the interface to be adapted to different fabric protocols. The FP is Utopia-1, 2 and Utopia-3, IBM PRIZMA, and PowerX (Csix-L0) compatible.
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The FP can be configured to run at any frequency up to 110MHz, and the receive and transmit data buses are 16 or 32 bits wide. This allows a wide range of supported bandwidths to and from the switching fabric, all the way up to 3200Mbps full duplex bandwidth.
Buffer Management Unit
The Buffer Management Unit (BMU) interfaces the C-5 NP to external pipeline architecture, Single Data Rate Synchronous DRAM. The external memory is partitioned and used as buffers for receiving and transmitting data between CPs, the FP, and the XP. It is also used as second level storage in the XP memory hierarchy. The interface to an array of SDRAM chips is 139bits wide, composed of 128 data bits, two internal control bits, and nine SECDED (single error correction-double error detection) ECC (error correction code) bits. The interface is compliant with the PC100 standard and operates at up to 125MHz with 3.3V LVTTL-compatible inputs and outputs. The refresh period, Trcd, Tcas, Trp, Tmrd, and Trc are configurable via boot time configuration (see the C-5 Network Processor Architecture Guide for more details). The C-5 NP uses auto-refresh mode and the interface, (which is not configurable), transfers four bits of data for each read and write using a sequential burst type. Some of these parameters are programmed into the SDRAMs' mode register and can be applied only once per power cycle. The ECC functionality can be enabled or disabled via configuration register writes. If needed, the interface can narrowed to 128bits by disabling ECC and providing board pull-ups for the two control bits and nine ECC bits. This is useful if DIMMs are used in the board design. If individual SDRAM parts are used, x16 and x32 are supported. The BMU supports SDRAM devices that use 12 address lines. Internal address calculation paths limit the maximum memory size to 128MBytes. Only one physical bank of SDRAM is supported.
Table Lookup Unit
The Table Lookup Unit (TLU) performs table lookups in external SRAM. It can also be used for statistics accumulation and retrieval and as general data storage. The TLU
C5NP
External Mode
25
simultaneously supports multiple application-defined tables and multiple search strategies, such as those needed for routing, circuit switching, and QoS lookup tasks. The C-5 NP uses external 64bit wide ZBT Pipelined Bursting Static RAM (SRAM) modules (at frequencies to 133MHz) for storage of its tables. These modules allow implementation of tables with 220 x 64bit entries at a cycle time of up to 7.5 nanoseconds using 4Mbit SRAM technology. The maximum amount of memory supported by the TLU is 32MBytes in four banks.
Table 4 TLU SRAM Configurations
SRAM TECHNOLOGY* MIN TABLE SIZE (ONE BANK) NO. OF PARTS MAXIMUM TABLE SIZE (FOUR BANKS) NO. OF PARTS
Freescale Semiconductor, Inc...
1Mbit (32k x 32) 2Mbit (64k x 32) 4Mbit (256k x 18) 8Mbit (512k x 18 16Mbit (1M x 18)
*
256kBytes 512kBytes 2MBytes 4MBytes 8MBytes
2 2 4 4 4
1MBytes 2MBytes 8MBytes 16MBytes 32MBytes
8 8 16 16 16
For (n x 32) parts, divide total memory and number of parts by two.
External Mode Queue Management Unit
There is support for external devices. Refer to the C-5 Archictecture Guide.
The Queue Management Unit (QMU) autonomously manages a number of application-defined descriptor queues. It handles inter-CP and inter-C-5 NP descriptor flows by providing switching and buffering. It also performs descriptor replication for multicast applications. A number of queues can be assigned to each CPRC for QoS-based services. The QMU provides a queuing engine internal to the chip and uses external SRAM to store the descriptors. Scheduling is done by the CPs. The QMU supports up to 512 queues and 16, 384 descriptor buffers. A descriptor buffer holds an application-defined "descriptor" , which is a structure that defines the payload buffer handle and other attributes of the forwarded cell or packet. The QMU's external SRAM interface uses ZBT synchronous SRAMs organized in a single bank of up to 128k, 32bit words. This interface runs at half (1/2) the core clock frequency.
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CHAPTER 1: FUNCTIONAL DESCRIPTION
Freescale Semiconductor, Inc...
C5NP
C5NPD0-DS/D
Chapter 2
Rev 04
SIGNAL DESCRIPTIONS
Freescale Semiconductor, Inc...
Signal Summary
There are ten functional groupings of signals in the C-5 network processor:
* * *
Clock -- 11 pins Channel Processors (CP0 - CP15) -- 16x7 = 112 pins Executive Processor (XP) -- 57 pins - PCI Interface -- 50 pins - PROM Interface -- 4 pins - Serial Bus Interface -- 2 pins - General System Interface -- 1 pin
* * * * * * *
Fabric Processor (FP) -- 80 pins Buffer Management Unit (BMU) -- 161 pins Table Lookup Unit (TLU) -- 100 pins Queue Management Unit (QMU) -- 55 pins Power -- 233 pins Test -- 18 pins No connection (NC) -- 11 pins
Two of the sections (CPs and FP) are configurable, depending on the type of device being implemented.
Pinout Diagram
The C-5 NP contains 838 pins as shown in Figure 2. These pin numbers are referenced throughout the remaining chapter.
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CHAPTER 2: SIGNAL DESCRIPTIONS
Figure 2 Pin Locations (Bottom View)
C-5 Network Processor
AC AB AA Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
838 Total Pins
Freescale Semiconductor, Inc...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Pin Descriptions Grouped by Function
The C-5 NP pins are categorized in groups, reflecting interfaces to the chip:
* * *
Clock Signals CP Interface Signals Executive Processor System Interface Signals
C5NP
Pin Descriptions Grouped by Function
29
Freescale Semiconductor, Inc...
* * * * * * *
LVTTL and LVPECL Specifications
Fabric Processor Interface Signals BMU SDRAM Interface Signals TLU SRAM Interface Signals QMU SRAM Interface Signals Power Supply Signals Test Signals No Connection Pins
C-5 NP pins are the following types:
* *
Low Voltage TTL-Compatible (LVTTL). The C-5 NP's LVTTL pins conform to the JEDEC JESD8-B specification. Low Voltage Positive Emitter Coupled Logic (LVPECL). The C-5 NP's LVPECL pins conform to the JEDEC JESD8-2 specification.
Clock Signals
Table 5 describes the C-5 NP clock signals.
Table 5 Clock and Reference Signals
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
SCLK* SCLKX* CCLK0 CCLK1 CCLK2 CCLK3 CCLK4 CCLK5 CCLK6 CCLK7
H15 G15 K12 J13 J15 I12 I14 H13 K14 K16
1 1 1 1 1 1 1 1 1 1
LVPECL LVPECL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL
I I I I I I I I I I
Core Clock Rate (Differential) 1_544MHZ_CLK (T1) 2_048MHZ_CLK (E1) 34_368MHZ_CLK (E3) 44_736MHZ_CLK (T3) 50MHZ_CLK (100Mbit Ethernet) 106_25MHZ_CLK (Fibre Channel) 125MHZ_CLK (Gigabit Ethernet) 155_52MHZ_CLK (OC-3)
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CHAPTER 2: SIGNAL DESCRIPTIONS
Table 5 Clock and Reference Signals (continued)
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
CPREF
TOTAL
*
L13
1
11
LVPECL
I
Reference
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SCLK and SCLKX must not be AC-coupled. The frequencies specified for CCLK0 - CCLK7 allow full flexibility for the C-5 NP. Clock inputs associated with a specific protocol should be wired to ground when that protocol is not used by the C-5 NP. It is also possible to use one or more CCLKn inputs for other frequencies. Contact your C-Port representative for more information. If any of the CPs are configured for LVPECL operation (OC3) using the pin mode registers, then CPREF must be wired to an external reference, as specified in Table 36 on page 68. If none of the CPs are configured for LVPECL operation, then the CPREF pin can be left unconnected. It is acceptable to tie the CPREF pin high or low through a resistor, or into the specified reference, but this is not required.
CP Interface Signals
The C-5 NP's 16 CPs support various network physical interfaces, providing a serial interface to the PHY layer. Interfaces are configured via bits in the C-5 NP register set. Many interfaces are possible by programming the configuration registers. CPs can be used individually or in a cluster (four CPs) to implement the various interfaces. Table 6 provides a quick reference of all the CP pins organized by clusters. There are seven physical I/O pins associated with each CP. All pins are capable of receiving data, with some configurable to be input clocks, output clocks, or data drivers. In addition, pairs of pins can be configured as differential pairs for LVPECL compatibility. In the case of RMII, OC-3, DS1, and DS3, the drivers and receivers at the pin are locally configured to match the relevant PHY or Framer chip. OC-12 uses the aggregation of four CPs (one cluster), while GMII and Ten Bit Interface (TBI) can use either eight CPs (four for receive and four for transmit) or four CPs that share the transmit and receive functions for non-wire speed applications. During CP aggregation, all 28 pins associated with a cluster are routed to all of the Serial Data Processors (SDPs) in that cluster. This allows round-robin usage of portions of the SDPs, with each getting access to the necessary I/O pins. The signals for the following CP physical interfaces are included in this section:
* * *
C5NP
DS1/T1 Framer Interface Configuration 10/100 Ethernet (RMII) Configuration Gigabit Ethernet (GMII) Configuration
Pin Descriptions Grouped by Function
31
* * *
Gigabit Ethernet and Fibre Channel TBI Configuration SONET OC-3 Transceiver Interface Configuration SONET OC-12 Transceiver Interface Configuration
Table 6 CP Physical Interface Signals and Pins (Grouped by Clusters)
Freescale Semiconductor, Inc...
CP CLUSTER 1 SIGNAL PIN #
CP CLUSTER 2 SIGNAL PIN #
CP CLUSTER 3 SIGNAL PIN #
CP CLUSTER 4 SIGNAL PIN #
CP0_0 CP0_1 CP0_2 CP0_3 CP0_4 CP0_5 CP0_6 CP1_0 CP1_1 CP1_2 CP1_3 CP1_4 CP1_5 CP1_6 CP2_0 CP2_1 CP2_2 CP2_3 CP2_4 CP2_5 CP2_6 CP3_0 CP3_1
AC28 AC26 AC24 AC22 AC20 AC18 AC16 AC02 AC04 AC06 AC08 AC10 AC12 AC14 AB29 AB28 AB27 AB26 AB25 AB24 AB23 AB01 AB02
CP4_0 CP4_1 CP4_2 CP4_3 CP4_4 CP4_5 CP4_6 CP5_0 CP5_1 CP5_2 CP5_3 CP5_4 CP5_5 CP5_6 CP6_0 CP6_1 CP6_2 CP6_3 CP6_4 CP6_5 CP6_6 CP7_0 CP7_1
AB22 AB21 AB20 AB19 AB18 AB17 AB16 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AA28 AA26 AA24 AA22 AA20 AA18 AA16 AA02 AA04
CP8_0 CP8_1 CP8_2 CP8_3 CP8_4 CP8_5 CP8_6 CP9_0 CP9_1 CP9_2 CP9_3 CP9_4 CP9_5 CP9_6 CP10_0 CP10_1 CP10_2 CP10_3 CP10_4 CP10_5 CP10_6 CP11_0 CP11_1
Z29 Z28 Z27 Z26 Z25 Z24 Z23 Z01 Z02 Z03 Z04 Z05 Z06 Z07 Z22 Z21 Z20 Z19 Z18 Z17 Z16 Z08 Z09
CP12_0 CP12_1 CP12_2 CP12_3 CP12_4 CP12_5 CP12_6 CP13_0 CP13_1 CP13_2 CP13_3 CP13_4 CP13_5 CP13_6 CP14_0 CP14_1 CP14_2 CP14_3 CP14_4 CP14_5 CP14_6 CP15_0 CP15_1
Y28 Y26 Y24 Y22 Y20 Y18 Y16 Y02 Y04 Y06 Y08 Y10 Y12 Y14 X29 X28 X27 X26 X25 X24 X23 X01 X02
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CHAPTER 2: SIGNAL DESCRIPTIONS
Table 6 CP Physical Interface Signals and Pins (Grouped by Clusters) (continued)
CP CLUSTER 1 SIGNAL PIN # CP CLUSTER 2 SIGNAL PIN # CP CLUSTER 3 SIGNAL PIN # CP CLUSTER 4 SIGNAL PIN #
CP3_2 CP3_3 CP3_4 CP3_5 CP3_6
AB03 AB04 AB05 AB06 AB07
CP7_2 CP7_3 CP7_4 CP7_5 CP7_6
AA06 AA08 AA10 AA12 AA14
CP11_2 CP11_3 CP11_4 CP11_5 CP11_6
Z10 Z11 Z12 Z13 Z14
CP15_2 CP15_3 CP15_4 CP15_5 CP15_6
X03 X04 X05 X06 X07
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DS1/T1 Framer Interface Configuration Table 7 describes the serial framer interface signals. For each CP (0-15), you can implement one serial Framer interface.
Table 7 DS1/T1 Framer Interface Signals
SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION
CPn_0 CPn_1 CPn_2 CPn_3 CPn_4 CPn_5 CPn_6
TOTAL PINS
*
Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6
1 1 1 1 1 1 1 7
LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL nc
O I O O I I nc
TCLK RCLK TData TFrame RData RFrame nc
Transmit Clock (1.544MHz) Receive Clock (1.544MHz) Transmit Data Transmit Frame Synchronization Receive Data Receive Frame Synchronization nc
n can be from 0 to 15. See Table 6. Reference Table 6 for pin numbers for the actual cluster(s) you are configuring.
10/100 Ethernet (RMII) Configuration Table 8 describes the 10/100BASE-T Ethernet Reduced Media Independent Interface (RMII) signals. For each CP (0-15), you can implement one 10/100 Ethernet interface.
C5NP
Pin Descriptions Grouped by Function
33
Table 8 10/100 Ethernet Signals
SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION
CPn_0 CPn_1
Table 6 Table 6
1 1
LVTTL LVTTL
O I
REF_CLK CRS_DV
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CPn_2 CPn_3 CPn_4 CPn_5 CPn_6
TOTAL PINS
*
Table 6 Table 6 Table 6 Table 6 Table 6
1 1 1 1 1 7
LVTTL LVTTL LVTTL LVTTL LVTTL
O O I I O
TXD(0) TXD(1) RXD(0) RXD(1) TX_EN
Transmit and Receive Clock (50MHz) Carrier Sense (CRS)/ Receive Data Valid (RX_DV). CRS indicates that traffic is on the link, and is asserted if the signal is a 1 or an alternating 1010... RX_DV indicates that a receive frame is in progress and the data present on the RXD pins is valid. It is asserted if this signal is a 1 for more than one cycle. Transmit Data 0 (first on wire) Transmit Data 1 (second on wire) Receive Data 0 (first on wire) Receive Data 1 (second on wire) Transmit Enable. When asserted, the data on TXD is encoded and transmitted on the twisted pair cable.
n can be from 0 to 15. See Table 6.
Gigabit Ethernet (GMII) Configuration Gigabit Ethernet Media Independent Interface (GMII) is configured in one of two ways: 1 Use one CP cluster when density is more important than wire-speed performance because you can then implement up to four Gigabit Ethernet ports per C-5 NP. 2 Use two CP clusters for wire-speed performance and additional processing power. You can implement up to two Gigabit Ethernet ports per C-5 NP. Table 9 lists the possible CP cluster combinations you can use and Figure 3 shows receive and transmit pin configurations by cluster. Table 10 lists the signals and pinouts for Gigabit Ethernet (GMII).
Table 9 Transmit and Receive Pin Combinations for Gigabit Ethernet and Fibre Channel
CLUSTER SINGLE CLUSTER MODE (TBI OR GMII) TWO CLUSTER MODE (GMII)*
0 1 2 3
*
Port 1 Tx and Rx Port 2 Tx and Rx Port 3 Tx and Rx Port 4 Tx and Rx
Port 1 Tx Port 1 Rx Port 2 Tx Port 2 Rx
The Two Cluster Mode column lists typical configurations. Any cluster can be set up to either receive or transmit. So you could configure a dual cluster mode where cluster 0 receives and cluster 3 transmits. V 04
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CHAPTER 2: SIGNAL DESCRIPTIONS
Figure 3 GMII/TBI Transmit and Receive Pin Configurations
Single Cluster Mode Pin Configuration Tx Two Cluster Mode Pin Configuration
Cluster 0
Rx Tx
} Port 1 } Port 2 } Port 3 } Port 4
Tx
Cluster 0
Rx
nc
Tx
Freescale Semiconductor, Inc...
Cluster 1
Rx Tx
Cluster 1
nc
Rx Tx
Cluster 2 Cluster 3
Rx Tx Rx
Cluster 2 Cluster 3 nc = not connected
Rx
nc
Tx
nc
Rx
} }
Port 1
Port 2
The unused CP pins in the two cluster configurations should be wired to ground using a resistor.
Table 10 Gigabit Ethernet (GMII/MII) Signals One Cluster Example
SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION
CPn_0 CPn_1 CPn_2 CPn_3 CPn_4 CPn_5 CPn_6 CPn+1_0 CPn+1_1 CPn+1_2 CPn+1_3
Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1
LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL nc LVTTL LVTTL LVTTL
O I O O O O O nc I O O
T_CLK TCLKI TXD(0) TXD(1) TXD(2) TXD(3) TX_EN nc COL TXD(4) TXD(5)
GMII Transmit Clock (125MHz). This clock is used to synchronize the transmit data. MII transmit clock. Transmit data aligned to this clock input from phy in MII mode. 25 Mhz in 100BaseT, 2.5 in Mhz in 10BaseT Transmit Data (byte-wide data, least significant bit) Transmit Data Transmit Data Transmit Data Transmit Enable. When asserted, the data on TXD is encoded and transmitted on the twisted pair cable. nc Collision. Asserted when both RX_DV and TX_EN are valid during half duplex operation. Transmit Data Transmit Data
C5NP
Pin Descriptions Grouped by Function
35
Table 10 Gigabit Ethernet (GMII/MII) Signals One Cluster Example (continued)
SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION
CPn+1_4 CPn+1_5 CPn+1_6
Table 6 1 Table 6 1 Table 6 1
LVTTL LVTTL LVTTL
O O O
TXD(6) TXD(7) TX_ER
Transmit Data Transmit Data (byte-wide receive data, most significant bit) Transmit Error. Asserting TX_ER when TX_EN is a 1 causes transmission of the designated "bad code" in lieu of the normal encoded data on the twisted pair data. nc Receive Clock (125MHz) Receive Data (byte-wide receive data, least significant bit) Receive Data Receive Data Receive Data Receive Data Valid. Indicates that there is a receive frame in progress and that the data present on the RXD signals is valid. nc Carrier Sense. Indicates traffic is on the link. CRS is asserted when a non-idle condition is detected on the receive data stream. CRS is deasserted when an end of frame or idle condition is detected. Receive Data Receive Data Receive Data Receive Data (most significant bit) Receive Error Detected. Indicates that there has been an error received in the receive frame.
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CPn+2_0 CPn+2_1 CPn+2_2 CPn+2_3 CPn+2_4 CPn+2_5 CPn+2_6 CPn+3_0 CPn+3_1
Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1
nc LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL nc LVTTL I I I I I I nc I
nc RCLK RXD(0) RXD(1) RXD(2) RXD(3) RX_DV nc CRS
CPn+3_2 CPn+3_3 CPn+3_4 CPn+3_5 CPn+3_6
TOTAL PINS
*
Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 28
LVTTL LVTTL LVTTL LVTTL LVTTL
I I I I I
RXD(4) RXD(5) RXD(6) RXD(7) RX_ER
n can be 0, 4, 8, or 12. Reference Table 6 for pin numbers for the actual cluster(s) you are configuring.
Gigabit Ethernet and Fibre Channel TBI Configuration 1000BASE-T Gigabit Ethernet and Fibre Channel TBI is implemented in much the same way as Gigabit Ethernet (GMII). Table 9 shows the possible CP pin combinations you can
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CHAPTER 2: SIGNAL DESCRIPTIONS
use and Figure 3 shows receive and transmit pin configurations by cluster. Table 11 shows the signals and pinouts for a single cluster for Gigabit Ethernet and Fibre Channel TBI. The unused pins for the two cluster configurations should be wired down using a resistor.
Table 11 Gigabit Ethernet and Fibre Channel TBI Signals Example
SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION
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CPn_0 CPn_1 CPn_2 CPn_3 CPn_4 CPn_5 CPn_6 CPn+1_0 CPn+1_1 CPn+1_2 CPn+1_3 CPn+1_4 CPn+1_5 CPn+1_6 CPn+2_0 CPn+2_1 CPn+2_2 CPn+2_3 CPn+2_4 CPn+2_5 CPn+2_6 CPn+3_0 CPn+3_1
Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1
LVTTL nc LVTTL LVTTL LVTTL LVTTL LVTTL nc nc LVTTL LVTTL LVTTL LVTTL LVTTL nc LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL nc LVTTL
O nc O O O O O nc nc O O O O O nc I I I I I I nc I
TCLK nc TXD(9) TXD(8) TXD(7) TXD(6) TXD(1) nc nc TXD(5) TXD(4) TXD(3) TXD(2) TXD(0) nc RCLK RXD(9) RXD(8) RXD(7) RXD(6) RXD(1) nc RCLKN
Transmit Clock (125MHz). This clock is used to synchronize the transmit data. nc Transmit Data (ten bits wide, last on wire) Transmit Data Transmit Data Transmit Data Transmit Data nc nc Transmit Data Transmit Data Transmit Data Transmit Data Transmit Data (ten bits wide, first on wire) nc Receive Clock (62.5 MHz) Receive Data (ten bits wide, last on wire) Receive Data Receive Data Receive Data Receive Data nc Receive Clock Inverted
C5NP
Pin Descriptions Grouped by Function
37
Table 11 Gigabit Ethernet and Fibre Channel TBI Signals Example (continued)
SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION
CPn+3_2 CPn+3_3 CPn+3_4 CPn+3_5 CPn+3_6
TOTAL PINS
*
Table 6 1 Table 6 1 Table 6 1 Table 6 1 Table 6 1 28
LVTTL LVTTL LVTTL LVTTL LVTTL
I I I I I
RXD(5) RXD(4) RXD(3) RXD(2) RXD(0)
Receive Data Receive Data Receive Data Receive Data Receive Data (ten bits wide, first on wire)
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n can be 0, 4, 8, or 12 Reference Table 6 for pin numbers for the actual cluster(s) you are configuring.
SONET OC-3 Transceiver Interface Configuration Table 12 describes the SONET Optical Carrier (OC) 3 transceiver interface signals. For each CP (0-15), you can implement a single OC-3 interface.
Table 12 OC-3 Signals
SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION
CPn_0 CPn_1 CPn_2 CPn_3 CPn_4 CPn_5 CPn_6
TOTAL PINS
*
Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6
1 1 1 1 1 1 1 7
LVPECL I LVPECL I LVPECL O LVPECL O LVPECL I LVPECL I LVPECL I
RCLK_H RCLK_L TXD_H TXD_L RXD_H RXD_L SIGNAL_DET
Receive Clock noninverted side of pair (155.52MHz) Receive Clock inverted side of pair (155.52MHz) Transmit Data noninverted side of pair Transmit Data inverted side of pair Receive Data noninverted side of pair Receive Data inverted side of pair A light level above a certain threshold is present at the optical receiver - single ended LVPECL.
n can be from 0 to 15. Reference Table 6 for pin numbers for the actual cluster(s) you are configuring.
SONET OC-12 Transceiver Interface Configuration SONET Optical Carrier (OC) 12 is implemented by using one cluster of CPs. At any time, a CP within a cluster spends half its time performing receive functions, and the other half performing transmit functions. Table 13 shows a CP Cluster configured for one OC-12 interface.
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CHAPTER 2: SIGNAL DESCRIPTIONS
Table 13 OC-12 Signals Example
SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION
CPn_0 CPn_1
Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6 Table 6
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL nc nc LVTTL LVTTL LVTTL LVTTL nc nc LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL nc nc LVTTL LVTTL LVTTL
O I O O O O 0 nc nc O O O O nc nc I I I I I I nc nc I I I
TCLK TCLK1 TXD(0) TXD(1) TXD(2) TXD(3) 00F nc nc TXD(4) TXD(5) TXD(6) TXD(7) nc nc RCLK RXD(0) RXD(1) RXD(2) RXD(3) FP nc nc RXD(4) RXD(5) RXD(6)
Deskewed Transmit Clock (77.76MHz). This clock is used to synchronize the transmit data. Transceiver Transmit Clock. This clock sets the frequency of the transmit data and is typically sourced by the PHY chip. Transmit Data (byte-wide data, least significant bit) Transmit Data Transmit Data Transmit Data Out of Frame nc nc Transmit Data Transmit Data Transmit Data Transmit Data (byte-wide data, most significant bit) nc nc Receive Clock (77.76MHz) Receive Data (byte-wide receive data, least significant bit) Receive Data Receive Data Receive Data Frame Synchronization Pulse. This is valid during the third A2 of the receive SONET frame. nc nc Receive Data Receive Data Receive Data
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CPn_2 CPn_3 CPn_4 CPn_5 CPn_6 CPn+1_0 CPn+1_1 CPn+1_2 CPn+1_3 CPn+1_4 CPn+1_5 CPn+1_6 CPn+2_0 CPn+2_1 CPn+2_2 CPn+2_3 CPn+2_4 CPn+2_5 CPn+2_6 CPn+3_0 CPn+3_1 CPn+3_2 CPn+3_3 CPn+3_4
C5NP
Pin Descriptions Grouped by Function
39
Table 13 OC-12 Signals Example (continued)
SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL SIGNAL DESCRIPTION
CPn+3_5 CPn+3_6
TOTAL PINS
Table 6 Table 6
1 1 28
LVTTL nc
I nc
RXD(7) nc
Receive Data (most significant bit) nc
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*
n can be 0, 4, 8, or 12 Reference Table 6 for pin numbers for a different cluster.
Executive Processor System Interface Signals
The XP's system interface manages the supervisory controls for the network interfaces, as well as the set of pins that provide interfaces to other components in the system that are not memories or network interfaces. It is also the primary interface used for initializing the C-5 NP after reset. The XP signals include PCI signals, Serial interface signals, and PROM interface signals. PCI Signals The PCI can be configured to support a 32bit PCI capable of operating at either 33MHz or 66MHz. The PCI is fully compliant with PCVI Specification revision 2.1. Table 14 describes the PCI signals.
Table 14 PCI Signals
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
PAD0 - PAD31
T22, R21, P21, T21, R20, P20, T20, 32 R19, Q20, S20, R18, P19, T19, R17, P18, T18, R16, Q18, S18, S16, P17, T17, R15, P16, T16, S14, Q16, T15, R14, P15, T14, Q14 N21, N20, M20, O20 4
PCI
I/O
Multiplexed Address/Data Bus. These signals are multiplexed address and data bits. The C-5 NP receives addresses as target and drives addresses as master. It drives the data and receives read data as master. Command byte enables. These signals are multiplexed command and byte enabled signals. The C-5 NP receives byte enables as target and drives byte enables as master. Parity. This signal carries even parity for AD and CBE# pins. It has the same receive and drive characteristics as the address and data bus, except that it is one PCI cycle later. Cycle frame Target ready for data transfer Initiator ready for data transfer
PCBEX0 - PCBEX3
PCI
I/O
PPAR
P14
1
PCI
I/O
PFRAMEX PTRDYX PIRDYX
K20 L20 L19
1 1 1
PCI PCI PCI
I/O I/O I/O
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CHAPTER 2: SIGNAL DESCRIPTIONS
Table 14 PCI Signals (continued)
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
PSTOPX PDEVSELX PPERRX PSERRX PCLK PRSTX PREQX PGNTX PIDSEL PINTA
TOTAL PINS
K18 N18 M18 L18 L15 N17 L17 N19 O18 O16
1 1 1 1 1 1 1 1 1 1 50
PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI
I/O I/O I/O I/O I I O I I O
Target transaction stop request Target device selected Bus parity error System error Bus clock Bus reset Initiator bus request (arbitration) Initiator bus grant (arbitration) Initialization device select Interrupt
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Serial Interface Signals The Serial interface is a bidirectional two-wire serial bus. It can use one of the following formats: 1 An 8bit data format followed by an acknowledge bit, which supports transfers at up to 400kbps (low speed). 2 a 16bit IEEE 802.3 MDIO data format with 10bits of addressing, which supports transfers up to 25MHz (high speed). The signals and pins are identical for both the high and low speed protocols. Which of the two data rates used is selected by the state of the PROM interface's SPLD signal that is asserted while the PROM interface is idle. When SPLD is asserted HI the low speed serial bus protocol is selected and when SPLD is asserted LOW the MDIO protocol is selected. The bus only supports a single master hierarchy that can operate as either a receiver or a transmitter. The bus also supports collision detection and arbitration, and an integrated addressing and data-transfer protocol. Both SIDA and SICL are bidirectional lines that are connected, through a pull-up resistor, to a positive supply voltage. When the bus is free, both lines are HIGH. The output stages
C5NP
Pin Descriptions Grouped by Function
41
of the devices connected to the bus must have either an open-drain or open-collector in order to perform the wired-AND function required for its arbitration mechanism.
Table 15 Serial Port Signals
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
SICL
O14 N14
1 1 2
LVTTL LVTTL
I/O I/O
Serial Clock line Serial Data line
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SIDA
TOTAL PINS
PROM Interface Signals The PROM interface is a low speed I/O port that allows the C-5 NP to communicate through external logic to PROM. The PROM clock is 1/2 to 1/16 the core clock rate. The maximum PROM size is 4MBytes x 16, and configuration is required. The PROM signals are listed in Table 16.
Table 16 PROM Interface Signals
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
SPDO SPDI SPLD
N15 N16 M16
1 1 1
LVTTL LVTTL LVTTL
O I O
Serial Data Out Serial Data In When load is asserted on a positive clock edge, the external logic performs a parallel load. On each positive clock edge when load is de-asserted, the shift registers shift. When the PROM interface is idle: * if SPLD is asserted HI it indicates low speed serial protocol,
*
SPCK
TOTAL PINS
if asserted LOW it indicates MDIO serial protocol.
M14
1 4
LVTTL
O
Clock
Figure 4 shows the connections between the PROM Interface and external board logic. The application is required to provide an external shift register with parallel-in and parallel-out capabilities, and a parallel load register. Both devices should be
V 04
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CHAPTER 2: SIGNAL DESCRIPTIONS
positive-edge-triggered and perform a parallel load whenever SPLD is asserted. When SPLD is deasserted the shift register shifts.
Figure 4 PROM Interface Diagram
C-5 Network Processor 21 0 PROM_ADDR<21:1> CE External Logic SPDO 21 21 6 1 0 SPDI 21 60
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15 31 PROM _H_Word PROM _Return_Data
Internal Shift Register
16 15 0 PROM _LO_Word
External Shift Register 21 0 PROM_ADDR<21:1> CE 21 1 PROM 16
PROM Clock Gen. SPCLK PROM Sequencer SPLD
PROM_Data
The PROM interface operates in the following manner: Two accesses are piplined together to execute one 32-bit fetch. The steps are shown in Figure 5. 1 The PROM_ADDR is loaded into the network processor internal shift register. 2 The PROM_ADDR is shifted into the external shift register for 22 SPCLK cycles. 3 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external presentation register. 4 SPLD is deasserted for 22 SPCLK cycles. The PROM presents the first 16bit PROM_DATA. At the same time, the next PROM_ADDR is shifted into the external shift register. 5 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external presentation register and the first PROM_DATA into the external shift register. 6 SPLD is deasserted for 22 SPCLK cycles, shifting the first PROM_DATA into the network processor internal shift register.
C5NP
Pin Descriptions Grouped by Function
43
7 SPLD is asserted for one SPCLK cycle, loading the first PROM_DATA into the network processor PROM_RETURN_DATA register and the second PROM_DATA into the external shift register. 8 SPLD is deasserted for 22 SPCLK cycles, shifting the second PROM_DATA into the network processor internal shift register.
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9 SPLD is asserted for one SPCLK cycle, loading the second PROM_DATA into the network processor PROM_RETURN_DATA register.
Figure 5 PROM Interface Timing Outline
XP PROM Interface outline SPLD SPDTO
`
`
`
`
`
A1
A2
A3
A4
A5
SPDTI XP PROM Interface detail
1 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8
D1
D2
D3
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1
2
3
4
5
6
7
SPCLK SPLD
SPDTO
x
A1
AAAAAAAAAAAAAA 20 19 18 17 16 15 14 13 12 11 10 9 8 7 A 6 AA 54 AA 32 A A CE 10
A2
A3
A4
1
2
The PROM_ADDR is loaded into the C-5's internal shift register. The PROM_ADDR is shifted into the external shift register. (SPCLK Rising Edge used for shifting)
3
5
The PROM_ADDR is loaded into the external presentation register.
The PROM_DATA is presenting.
4
The PROM_DATA is loaded into the external shift register. D1
x
DDDDDDDDD 15 14 13 12 11 10 9 8 7 DD 65 DD 43 DD 21 D 0 x x x x x x
D2
SPDTI
6
8
The PROM_DATA is shifted into the C-5's Internal shift register.
7
9
The PROM_DATA is loaded into the C-5's internal PROM_RETURN_DATA register.
General System Interface Signal Table 17 provides the signal for the Executive Processor reset power status and I/O clock. The C-5 NP can be powered up with the XP either running or with the XP in reset mode similar to the CPs. When the XP remains in reset mode, an external host can be used to control the initialization of the C-5 NP.
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CHAPTER 2: SIGNAL DESCRIPTIONS
Table 17 General System Interface Signal
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
XPUHOT
J19
1
LVTTL
I
Sample at Power On Reset determines if the XP RISC Core is held in reset. Low equals reset and High equals active. During normal operation, this is an external interrupt.
TOTAL PINS
1
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Fabric Processor Interface Signals
The FP consists of two logical signal interfaces: a receive data interface and a transmit data interface, each with its own control and clocking signals. The interface has the following characteristics:
* *
The interface clocks FRXCLK and FTXCLK can have a different frequency from the core C-5 NP clock frequency. The Fabric Data Processor (FDP) has synchronizing FIFOs at its interface boundary to allow for a fabric interface frequency from 10MHz to 110MHz. The receive clock FRXCLK and the transmit clock FTXCLK must share the same frequency. The synchronization logic internal to the FP requires related clock domains on the transmit and receive interfaces. Each of the two clocks can have different phase alignment, however, because they are generated externally.
Each data bus can be run at widths of 16 or 32 bits of data (FIN0 - FIN31 and FOUT0 FOUT31) per clock. The extra data pins in each configuration remain unused. The output pins are driven to a known state, and the input pins should also be pulled to a known state.
Table 18 Fabric Interface Signals
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
FIN0 - FIN31
W2, V1, T1, V2, U2, V3, T3, T2, W4, V4, V5, U4, T4, 32 W6, V6, U6, T5, T6, V7, T7, X8, W8, V8, V9, U8, X9, V10, U10, X10, W10, X11, V11 W28, V29, T29, V28, U28, V27, T27, T28, W26, V26, V25, U26, T26, W24, V24, U24, T25, T24, V23, T23, X22, W22, V22, V21, U22, X21, V20, U20, X20, W20, X19, V19 W14 W16 U12, W12, V12, X12, X13, V13, X14 32
LVTTL
I
Fabric Data Bus In
FOUT0 - FOUT31
LVTTL
O
Fabric Data Bus Out
FRXCLK FTXCLK FRXCTL0 - FRXCTL6
1 1 7
LVTTL LVTTL LVTTL
I I I, O
Receive Clock Transmit Clock Receive Control Signals
C5NP
Pin Descriptions Grouped by Function
45
Table 18 Fabric Interface Signals (continued)
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
FTXCTL0 - FTXCTL6
TOTAL PINS
U18, W18, V18, X18, X17, V17, X16
7 80
LVTTL
I, O
Transmit Control Signals
The following tables list the Fabric Interface pin mappings:
Freescale Semiconductor, Inc...
* * * *
RECEIVE SIGNALS C-5 NETWORK PROCESSOR I/O
Utopia1, Utopia2, Utopia3 ATM Mode mappings are listed in Table 19 Utopia1, Utopia2, Utopia3 PHY Mode mappings are listed in Table 20 PRIZMA Mode mappings are listed in Table 21 (PRIZMA mode is an example of Utopia3
PHY mode)
Power X Mode mappings are listed in Table 22
Table 19 Utopia1*, 2*, 3 ATM Mode, C-5 Network Processor to Fabric Interface Pin Mapping
TRANSMIT SIGNALS UTOPIA NOTE C-5 NETWORK PROCESSOR I/O UTOPIA NOTE
FRXCTL0 FRXCTL1 FRXCTL2 FRXCTL3 FRXCTL4 FRXCTL5 FRXCTL6
*
Output Input Input Input Input Input Input
RxEnb* RxClav RxSOC n/a n/a n/a RxPrty
Pullup or nc Pulldown Pulldown Pullup or Pulldown
FTXCTL0 FTXCTL1 FTXCTL2 FTXCTL3 FTXCTL4 FTXCTL5 FTXCTL6
Output Input Output nc nc nc Output
TxEnb* TxClav TxSOC nc nc nc TxPrty
Pullup or nc Pulldown Pulldown
cell size must be 4Byte aligned.
Table 20 Utopia1*, 2*, 3 PHY Mode, C-5 Network Processor to Fabric Interface Pin Mapping
RECEIVE SIGNALS C-5 NETWORK PROCESSOR I/O UTOPIA NOTE TRANSMIT SIGNALS C-5 NETWORK PROCESSOR I/O UTOPIA NOTE
FRXCTL0
Input
TxEnb*
Pullup
FTXCTL0
Input
RxEnb*
Pullup
V 04
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CHAPTER 2: SIGNAL DESCRIPTIONS
Table 20 Utopia1*, 2*, 3 PHY Mode, C-5 Network Processor to Fabric Interface Pin Mapping
RECEIVE SIGNALS C-5 NETWORK PROCESSOR I/O UTOPIA NOTE TRANSMIT SIGNALS C-5 NETWORK PROCESSOR I/O UTOPIA NOTE
FRXCTL1 FRXCTL2
Output Input Input Input Input Input
TxClav TxSOC n/a n/a n/a TxPrty
Pulldown or nc Pulldown Pullup or Pulldown Pullup or Pulldown Pullup or Pulldown
FTXCTL1 FTXCTL2 FTXCTL3 FTXCTL4 FTXCTL5 FTXCTL6
Output Output nc nc nc Output
RxClav RxSOC nc nc nc RxPrty
Pulldown or nc Pulldown
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FRXCTL3 FRXCTL4 FRXCTL5 FRXCTL6
*
cell size must be 4Byte aligned.
When configuring two C-5 network processors back-to-back using the Fabric Port, set up the transmit side of each C-5 network processor in Utopia ATM mode and the receive side of each C-5 network processor in Utopia PHY mode.
Table 21 PRIZMA Mode, C-5 Network Processor to Fabric Interface Pin Mapping
RECEIVE SIGNALS C-5 NETWORK PROCESSOR I/O UTOPIA NOTE TRANSMIT SIGNALS C-5 NETWORK PROCESSOR I/O UTOPIA NOTE
FRXCTL0
Input
TxEnb*
pulldown FTXCTL0 (not connected to fabric) nc Pulldown Pullup or Pulldown Pullup or Pulldown Pullup or Pulldown FTXCTL1 FTXCTL2 FTXCTL3 FTXCTL4 FTXCTL5 FTXCTL6
Input
RxEnb*
pulldown (not connected to fabric) nc Pulldown
FRXCTL1 FRXCTL2 FRXCTL3 FRXCTL4 FRXCTL5 FRXCTL6
Output Input Input Input Input Input
TxClav TxSOP n/a n/a n/a TxPrty or nc
Output Output nc nc nc Output
RxClav RxSOP nc nc nc RxPrty or nc
C5NP
Pin Descriptions Grouped by Function
47
Table 22 Power X Mode, C-5 Network Processor to Fabric Interface Pin Mapping
RECEIVE SIGNALS C-5 NETWORK PROCESSOR I/O POWER X NOTE TRANSMIT SIGNALS C-5 NETWORK PROCESSOR I/O POWER X NOTE
FRXCTL0 FRXCTL1
Input Input Input Input Input Input Input
RxCtrl[0] RxCtrl[1] RxCtrl[2] RxPrty[3] RxPrty[2] RxPrty[1] RxPrty[0]
Pulldown Pulldown Pulldown
FTXCTL0 FTXCTL1 FTXCTL2 FTXCTL3 FTXCTL4 FTXCTL5 FTXCTL6
Output Output Output Output Output Output Output
TxCtrl[0] TxCtrl[1] TxCtrl[2] TxPrty[3] TxPrty[2] TxPrty[1] TxPrty[0]
Pulldown or nc Pulldown or nc Pulldown or nc
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FRXCTL2 FRXCTL3 FRXCTL4 FRXCTL5 FRXCTL6
BMU SDRAM Interface Signals
The BMU and SDRAM interface signals are described in Table 23. The BMU is designed to support SDRAM devices with 12 address lines. All 139 data lines and all 12 address lines must be connected to the SDRAM in order for the BMU to be able to read and write external SDRAM properly.
Table 23 BMU SDRAM Interface Signals
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
MD0 - MD129
R29, Q28, P28, S28, R28, P29, R27, Q26, P26, S26, R26, P27, R25, Q24, P24, S24, R24, P25, S22, R23, R22, N29, M28, L28, J29, O28, N28, L29, K28, N27, M26, L26, J28, O26, N26, L27, K26, N25, M24, L24, J27, O24, N24, L25, K24, P22, M22, K22, J23, Q22, N23, L22, J25, O22, L23, J26, J22, P23, N22, L21, J24, B29, D29, F29, A28, C28, E28, G28, B28, D28, F28, B27, D27, F27, A26, C26, E26, B26, D26, F26, G26, B25, D25, F25, A24, C24, E24, B24, D24, F24, B23, D23, F23, G24, A22, C22, E22, B22, D22, F22, B21, D21, F21, A20, C20, E20, G22, B20, D20, F20, B19, D19, F19, A18, C18, E18, B18, D18, F18, G20, B17, D17, F17, A16, C16, E16, B16, D16, F16, B15
130
LVTTL
I/O
Data Lines In
MDECC0 - MDECC8 G16, F15, F14, E14, D15, D14, C14, B14, A14
9
LVTTL
I/O
Stored as data, ECC bits
V 04
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CHAPTER 2: SIGNAL DESCRIPTIONS
Table 23 BMU SDRAM Interface Signals (continued)
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
MA0 - MA11
H22, I22, H23, H24, I24, H25, H26, I26, H27, H28, I28, H29
12
LVTTL
O
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Address Outputs: A0-A11 are sampled during the ACTIVE command and READ/WRITE to select one location out of the memory array in the respective bank. The address inputs also provide the op-code during a LOAD MODE REGISTER command Bank Address Outputs: BA0 and BA1 define which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied Reserved Command Outputs: MRASX, MCASX, MWEX and MCSX define the command being entered. NOTE: MCSX is considered part of the command code. Command Outputs: MRASX, MCASX, MWEX and MCSX define the command being entered. MCSX is considered part of the command code. Command Outputs: MRASX, MCASX, MWEX and MCSX define the command being entered. MCSX is considered part of the command code. Chip Select: MCSX enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when MCSX is registered HIGH. MCSX provides the external bank selection on systems with multiple banks. MCSX is considered part of the command code. Input/Output Mask: MDQM is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when MDQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a high Z state (two-clock latency) when MDQM is sampled HIGH during the READ cycle. NOTE: MDQML is an identical copy of MDQM used to drive the loading on SDRAM configurations with 2 DQM pins.
MBA0 - MBA1
G18, H19
2
LVTTL
O
MCLK MCASX
I16 J21
1 1
nc LVTTL
nc O
MRASX
I20
1
LVTTL
O
MWEX
J20
1
LVTTL
O
MCSX
H20
1
LVTTL
O
MDQM MDQML
H21 G14
1 1
LVTTL LVTTL
O O
C5NP
Pin Descriptions Grouped by Function
49
Table 23 BMU SDRAM Interface Signals (continued)
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
MDCLK
J17
1
LVTTL
I
Clock: MDCLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of the MDCLK. MDCLK also increments the internal burst counter and controls the output registers.
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TOTAL PINS
161
TLU SRAM Interface Signals
The TLU SRAM interface supports up to 32MBytes of SRAM at frequencies to 133MHz using LVTTL signaling levels (in single bank-mode only) and SRAM technologies up to 64Mbits. The TLU SRAM interface signals are described in Table 24.
Table 24 TLU SRAM Interface Signals
SIGNAL NAME PIN # TOTAL TYPE I/O SIGNAL DESCRIPTION
TD0 - TD63
N1, L1, J1, H1, M2, K2, I2, G2, N2, L2, J2, H2, L3, J3, 64 H3, G4, 04, M4, K4, I4, L4, J4, H4, G6, N5, L5, J5, H5, N6, L6, I6, H6, K6, J6, M6, H7, L7, J7, H8, N8, M8, K8, I8, G8, N7, L8, J8, H9, L9, J9, J10, G10, P9, O8, L10, H10, O10, N9, L11, I10, M10, K10, J11, H11 R1, P1, S2, Q2, O2, R2, P2, R3, P3, N3, S4, Q4, R4, P4, 22 N4, R5, P5, S6, R6, Q6, P6, O6 T8, Q8, R7, P7 P8, R8, S8, T9 Q10, R9, S10, T10 M12 4 4 4 1 99 Table 25 Memory Bank Selection
LVTTL
I/O
TLU Memory Data
TA0 - TA21 TA18x - TA21x TCE0X - TCE3X TWE0X - TWE3X TCLKI
TOTAL PINS
LVTTL LVTTL LVTTL LVTTL LVTTL
O O O O I
TLU Memory Address Data Parity TLU Memory Chip Enable TLU Memory Write Enable TLU Clock Input
CHIP SELECT (SIGNALS TA18X THROUGH TA21X) BANK 1 SIZE CE2 CE2X BANK 2 CE2 CE2X BANK 3 CE2 CE2X BANK 4 CE2 CE2X
4Mbit 8Mbit 16Mbit
TA18x TA19x TA20x
TA19 TA20 TA21
TA18 TA19 TA20
TA19 TA20 TA21
TA18x TA19x TA20x
TA19x TA20x TA21x
TA18 TA19 TA20
TA19x TA20x TA21x
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CHAPTER 2: SIGNAL DESCRIPTIONS
QMU SRAM Interface Signals
The QMU signals are described in Table 26. The QMU's clock frequency is 1/2 the internal core clock frequency.
Table 26 QMU SRAM Interface Signals
SIGNAL NAME PIN # TOTAL TYPE I/O* SIGNAL DESCRIPTION
QCPAR
A10 G12 B10, C10, D10, E10, F10, B11, D11, F11, A12, B12, C12, D12, E12, B13, D13, F13 A8 D1, F1, F2, B2, C2, D2, E2, B3, D3, F3, A4, B4, C4, D4, E4, F4, B5, D5, F5, A6, B6, C6, D6, E6, F6, B7, D7, F7, C8, D8, E8, F8 B9 D9 F9 B8
1 1 16 1 32
nc LVTTL LVTTL LVTTL LVTTL
nc O O I/O I/O
Not used Clock Signal to the memory ICs Memory Address [15: 0] to the memory ICs Data parity Memory Data
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QCLK QCMD0 - QCMD15 QDPAR QDATA0 - QDATA31
QSFLOW QXCTRL0 QXCTRL1 QXRQST
TOTAL PINS
*
1 1 1 1 55
LVTTL LVTTL LVTTL nc
O O O nc
Not Used Rd/Wr (Read is true high, write is true low) Memory Address [16] to the memory ICs Reserved Note: Requires Pullup or Pulldown.
During normal (non-scan) operation.
Power Supply Signals
Table 27 Power Supply Signals
SIGNAL NAME PIN #
Power supply and ground signals are described in Table 27 and their pinouts are shown in Figure 6.
TOTAL
TYPE
SIGNAL DESCRIPTION
VDD
A3, A11, A15, A23, A27, C1, C5, C13, C17, C25, C29, 78 E3, E7, E15, E19, E27, G5, G9, G17, G21, G29, I7, I11, I19, I23, J12, K1, K9, K13, K21, K25, L14, M3, M11, M15, M23, M27, O1, O5, O13, O17, O25, O29, Q3, Q7, Q15, Q19, Q27, S5, S9, S17, S21, S29, U7, U11, U19, U23, W1, W9, W13, W21, W25, Y3, Y11, Y15, Y23, Y27, AA1, AA5, AA13, AA17, AA25, AA29, AC3, AC7, AC15, AC19, AC27
P
Core Supply Voltage (1.8V Input)
C5NP
Pin Descriptions Grouped by Function
51
Table 27 Power Supply Signals (continued)
SIGNAL NAME PIN # TOTAL TYPE SIGNAL DESCRIPTION
VDD33
A7, A19, C9, C21, E11, E23, F12, G1, G13, G25, H14, I3, 39 I15, I27, J16, K5, K17, K29, M7, M19, O9, O21, Q11, Q23, S1, S13, S25, U3, U15, U27, W5, W17, W29, Y7, Y19, AA9, AA21, AC11, AC23 A5, A9, A13, A17, A21, A25, A29, C3, C7, C11, C15, 116 C19, C23, C27, E1, E5, E9, E13, E17, E21, E25, E29, G3, G7, G11, G19, G23, G27, H12, H16, I1, I5, I9, I13, I17, I21, I25, I29, J14, J18, K3, K7, K11, K15, K19, K23, K27, L16, M1, M5, M9, M13, M17, M21, M25, M29, O3, O7, O11, O15, O19, O23, O27, Q1, Q5, Q9, Q13, Q17, Q21, Q25, Q29, S3, S7, S11, S15, S19, S23, S27, U1, U5, U9, U13, U17, U21, U25, U29, W3, W7, W11, W15, W19, W23, W27, Y1, Y5, Y9, Y13, Y17, Y21, Y25, Y29, AA3, AA7, AA11, AA15, AA19, AA23, AA27, AC1, AC5, AC9, AC13, AC17, AC21, AC25, AC29 234
P
I/O Supply Voltage (3.3V Input)
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VSS
P
Ground
TOTAL PINS
V 04
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CHAPTER 2: SIGNAL DESCRIPTIONS
Figure 6 Power and Ground Connections (Bottom View)
AC AB AA Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
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VSS (Ground) - 0.0V VDD (Core Supply) - 2.5V VDD33 (I/O Supply) - 3.3V
Other
Test Signals
Test signals are described in Table 28 and their pinouts are shown in Figure 6.
C5NP
Signals Grouped by Pin Number
53
Table 28 Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines
SIGNAL NAME PIN # TOTAL TYPE SIGNAL DESCRIPTION
JTCK JTMS*
T11 Z15
1 1
LVTTL LVTTL
Test Clock Test Mode Select. High selects modes as defined in the IEEE 1149.1 JTAG specification. Test Reset (low active) Test Data In Test Data Out Turns off all output drivers when High 1X or 2X Clock Mode Select. Low selects 1X, High selects 2X. Scan Enable. High enables scan test. Scan Out Pins
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JTRSTX JTDI JTDO JHIGHZ JCLKBYP JSE JS00-JS09
TOTAL PINS
*
X15 AB15 V15 T12 T13 S12 L12, N13, N12, P13, P12, Q12, R13, R12, R11, R10
1 1 1 1 1 1 10 18
LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL
According to the IEEE 1149.1 specification, the JTMS, JTRST, and JTDI pins must have internal pullups. While the C-5 NP does not currently have pads with pullups, customers can pull up these three pins on the board.
During JTAG, SCLK and SCLKX must remain as differential inputs.
No Connection Pins
Table 29 No Connection Pins
SIGNAL NAME PIN #
No connection pins are listed in Table 29.
TOTAL
TYPE
SIGNAL DESCRIPTION
NC1 - NC11
TOTAL PINS
I18, H17, H18, N10, P10, N11, P11, U14, V14, U16, V16
11 11
nc
Reserved for future functionality
Signals Grouped by Pin Number
The C-5 NP signals are listed by pin number in Table 30.
V 04
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CHAPTER 2: SIGNAL DESCRIPTIONS
Table 30 Signals Listed by Pin Number
PIN FUNCTION PIN FUNCTION PIN A 1-29 FUNCTION PIN FUNCTION
A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 C1 C2 C3 C4 C5 C6 C7 C8
Not present Not present VDD QDATA10 VSS QDATA19 VDD33 QDPAR Not present QDATA3 QDATA7 QDATA11 QDATA16 QDATA20 QDATA25 QXRQST VDD QDATA4 VSS QDATA12 VDD QDATA21 VSS QDATA28
A9 A10 A11 A12 A13 A14 A15 A16 B9 B10 B11 B12 B13 B14 B15 B16 C9 C10 C11 C12 C13 C14 C15 C16
VSS QCPAR VDD QCMD8 VSS MECC8 VDD MD123 QSFLOW QCMD0 QCMD5 QCMD9 QCMD13 MECC7 MD129 MD126 VDD33 QCMD1 VSS QCMD10 VDD MECC6 VSS MD124
A17 A18 A19 A20 A21 A22 A23 A24
B 1-29
VSS MD113 VDD33 MD103 VSS MD94 VDD MD84 MD120 MD116 MD110 MD107 MD100 MD97 MD90 MD87 VDD MD114 VSS MD104 VDD33 MD95 VSS MD85
A25 A26 A27 A28 A29
VSS MD74 VDD MD64 VSS
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B17 B18 B19 B20 B21 B22 B23 B24
C 1-29
B25 B26 B27 B28 B29
MD81 MD77 MD71 MD68 MD61
C17 C18 C19 C20 C21 C22 C23 C24
C25 CB26 C27 C28 C29
VDD MD75 VSS MD65 VDD
C5NP
Signals Grouped by Pin Number
55
Table 30 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN FUNCTION PIN D 1-29 FUNCTION PIN FUNCTION
D1 D2 D3 D4 D5 D6 D7 D8 E1 E2 E3 E4 E5 E6 E7 E8 F1 F2 F3 F4 F5 F6 F7 F8
QDATA0 QDATA5 QDATA8 QDATA13 QDATA17 QDATA22 QDATA26 QDATA29 VSS QDATA6 VDD QDATA14 VSS QDATA23 VDD QDATA30 QDATA1 QDATA2 QDATA9 QDATA15 QDATA18 QDATA24 QDATA27 QDATA31
D9 D10 D11 D12 D13 D14 D15 D16 E9 E10 E11 E12 E13 E14 E15 E16 F9 F10 F11 F12 F13 F14 F15 F16
QXCTRL0 QCMD2 QCMD6 QCMD11 QCMD14 MECC5 MECC4 MD127 VSS QCMD3 VDD33 QCMD12 VSS MECC3 VDD MD125 QXCTRL1 QCMD4 QCMD7 VDD33 QCMD15 MECC2 MECC1 MD128
D17 D18 D19 D20 D21 D22 D23 D24
E 1-29
MD121 MD117 MD111 MD108 MD101 MD98 MD91 MD88 VSS MD115 VDD MD105 VSS MD96 VDD33 MD86 MD122 MD118 MD112 MD109 MD102 MD99 MD92 MD89
D25 D26 D27 D28 D29
MD82 MD78 MD72 MD69 MD62
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E17 E18 E19 E20 E21 E22 E23 E24
F 1-29
E25 E26 E27 E28 E29
VSS MD76 VDD MD66 VSS
F17 F18 F19 F20 F21 F22 F23 F24
F25 F26 F27 F28 F29
MD83 MD79 MD73 MD70 MD63
V 04
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CHAPTER 2: SIGNAL DESCRIPTIONS
Table 30 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN FUNCTION PIN G 1-29 FUNCTION PIN FUNCTION
G1 G2 G3 G4 G5 G6 G7 G8 H1 H2 H3 H4 H5 H6 H7 H8 I1 I2 I3 I4 I5 I6 I7 I8
VDD33 TD7 VSS TD15 VDD TD23 VSS TD43 TD3 TD11 TD14 TD22 TD27 TD31 TD35 TD38 VSS TD6 VDD33 TD19 VSS TD30 VDD TD42
G9 G10 G11 G12 G13 G14 G15 G16 H9 H10 H11 H12 H13 H14 H15 H16 I9 I10 I11 I12 I13 I14 I15 I16
VDD TD51 VSS QCLK VDD33 MDQML SCLKX MECC0 TD47 TD55 TD63 VSS CCLK5 VDD33 SCLK VSS VSS TD59 VDD CCLK3 VSS CCLK4 VDD33 MCLK
G17 G18 G19 G20 G21 G22 G23 G24
H 1-29
VDD MBA0 VSS MD119 VDD MD106 VSS MD93 NC2 NC3 MBA1 MCSX MDQM MA0 MA2 MA3 VSS NC1 VDD MRASX VSS MA1 VDD MA4
G25 G26 G27 G28 G29
VDD33 MD80 VSS MD67 VDD
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H17 H18 H19 H20 H21 H22 H23 H24
I 1-29
H25 H26 H27 H28 H29
MA5 MA6 MA8 MA9 MA11
I17 I18 I19 I20 I21 I22 I23 I24
I25 I26 I27 I28 I29
VSS MA7 VDD33 MA10 VSS
C5NP
Signals Grouped by Pin Number
57
Table 30 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN FUNCTION PIN J 1-29 FUNCTION PIN FUNCTION
J1 J2 J3 J4 J5 J6 J7 J8 K1 K2 K3 K4 K5 K6 K7 K8 L1 L2 L3 L4 L5 L6 L7 L8
TD2 TD10 TD13 TD21 TD26 TD33 TD37 TD46 VDD TD5 VSS TD18 VDD33 TD32 VSS TD41 TD1 TD9 TD12 TD20 TD25 TD29 TD36 TD45
J9 J10 J11 J12 J13 J14 J15 J16 K9 K10 K11 K12 K13 K14 K15 K16 L9 L10 L11 L12 L13 L14 L15 L16
TD49 TD50 TD62 VDD CCLK1 VSS CCLK2 VDD33 VDD TD61 VSS CCLK0 VDD CCLK6 VSS CCLK7 TD48 TD54 TD58 JSO0 CPREF VDD PCLK VSS
J17 J18 J19 J20 J21 J22 J23 J24
K 1-29
MDCLK VSS XPUHOT MWEX MCASX MD56 MD48 MD60 VDD33 PSTOPX VSS PFRAMEX VDD MD47 VSS MD44 PREQX PSERRX PIRDYX PTRDYX MD59 MD51 MD54 MD39
J25 J26 J27 J28 J29
MD52 MD55 MD40 MD32 MD24
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K17 K18 K19 K20 K21 K22 K23 K24
L 1-29
K25 K26 K27 K28 K29
VDD MD36 VSS MD28 VDD33
L17 L18 L19 L20 L21 L22 L23 L24
L25 L26 L27 L28 L29
MD43 MD31 MD35 MD23 MD27
V 04
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CHAPTER 2: SIGNAL DESCRIPTIONS
Table 30 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN FUNCTION PIN M 1-29 FUNCTION PIN FUNCTION
M1 M2 M3 M4 M5 M6 M7 M8 N1 N2 N3 N4 N5 N6 N7 N8 O1 O2 O3 O4 O5 O6 O7 O8
VSS TD4 VDD TD17 VSS TD34 VDD33 TD40 TD0 TD8 TA9 TA14 TD24 TD28 TD44 TD39 VDD TA4 VSS TD16 VDD TA21 VSS TD53
M9 M10 M11 M12 M13 M14 M15 M16 N9 N10 N11 N12 N13 N14 N15 N16 O9 O10 O11 O12 O13 O14 O15 O16
VSS TD60 VDD TCLKI VSS SPCK VDD SPLD TD57 NC4 NC6 JSO2 JSO1 SIDA SPDO SPDI VDD33 TD56 VSS TCLKO VDD SICL VSS PINTA
M17 M18 M19 M20 M21 M22 M23 M24
N 1-29
VSS PPERRX VDD33 PCBEX2 VSS MD46 VDD MD38 PRSTX PDEVSELX PGNTX PCBEX1 PCBEX0 MD58 MD50 MD42 VDD PIDSEL VSS PCBEX3 VDD33 MD53 VSS MD41
M25 M26 M27 M28 M29
VSS MD30 VDD MD22 VSS
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N17 N18 N19 N20 N21 N22 N23 N24
O 1-29
N25 N26 N27 N28 N29
MD37 MD34 MD29 MD26 MD21
O17 O18 O19 O20 O21 O22 O23 O24
O25 O26 O27 O28 O29
VDD MD33 VSS MD25 VDD
C5NP
Signals Grouped by Pin Number
59
Table 30 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN FUNCTION PIN P 1-29 FUNCTION PIN FUNCTION
P1 P2 P3 P4 P5 P6 P7 P8 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 R1 R2 R3 R4 R5 R6 R7 R8
TA1 TA6 TA8 TA13 TA16 TA20 TA21X TCE0X VSS TA3 VDD TA11 VSS TA19 VDD TA19X TA0 TA5 TA7 TA12 TA15 TA18 TA20X TCE1X
P9 P10 P11 P12 P13 P14 P15 P16 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 R9 R10 R11 R12 R13 R14 R15 R16
TD52 NC5 NC7 JSO4 JSO3 PPAR PAD29 PAD23 VSS TWE0X VDD33 JSO5 VSS PAD31 VDD PAD26 TWE1X JSO9 JSO8 JSO7 JSO6 PAD28 PAD22 PAD16
P17 P18 P19 P20 P21 P22 P23 P24
Q 1-29
PAD20 PAD14 PAD11 PAD5 PAD2 MD45 MD57 MD14 VSS PAD17 VDD PAD8 VSS MD49 VDD33 MD13 PAD13 PAD10 PAD7 PAD4 PAD1 MD20 MD19 MD16
P25 P26 P27 P28 P29
MD17 MD8 MD11 MD2 MD5
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Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24
R 1-29
Q25 Q26 Q27 Q28 Q29
VSS MD7 VDD MD1 VSS
R17 R18 R19 R20 R21 R22 R23 R24
R25 R26 R27 R28 R29
MD12 MD10 MD6 MD4 MD0
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CHAPTER 2: SIGNAL DESCRIPTIONS
Table 30 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN FUNCTION PIN S 1-29 FUNCTION PIN FUNCTION
S1 S2 S3 S4 S5 S6 S7 S8 T1 T2 T3 T4 T5 T6 T7 T8 U1 U2 U3 U4 U5 U6 U7 U8
VDD33 TA2 VSS TA10 VDD TA17 VSS TCE2X FIN2 FIN7 FIN6 FIN12 FIN16 FIN17 FIN19 TA18X VSS FIN4 VDD33 FIN11 VSS FIN15 VDD FIN24
S9 S10 S11 S12 S13 S14 S15 S16 T9 T10 T11 T12 T13 T14 T15 T16 U9 U10 U11 U12 U13 U14 U15 U16
VDD TWE2X VSS JSE VDD33 PAD25 VSS PAD19 TCE3X TWE3X JTCK JHIGHZ JCLKBYP PAD30 PAD27 PAD24 VSS FIN27 VDD FRXCTL0 VSS NC8 VDD33 NC10
S17 S18 S19 S20 S21 S22 S23 S24
T 1-29
VDD PAD18 VSS PAD9 VDD MD18 VSS MD15 PAD21 PAD15 PAD12 PAD6 PAD3 PAD0 FOUT19 FOUT17 VSS FTXCTL0 VDD FOUT27 VSS FOUT24 VDD FOUT15
S25 S26 S27 S28 S29
VDD33 MD9 VSS MD3 VDD
Freescale Semiconductor, Inc...
T17 T18 T19 T20 T21 T22 T23 T24
U 1-29
T25 T26 TT27 T28 T29
FOUT16 FOUT12 FOUT6 FOUT7 FOUT2
U17 U18 U19 U20 U21 U22 U23 U24
U25 U26 U27 U28 U29
VSS FOUT11 VDD33 FOUT4 VSS
C5NP
Signals Grouped by Pin Number
61
Table 30 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN FUNCTION PIN V 1-29 FUNCTION PIN FUNCTION
V1 V2 V3 V4 V5 V6 V7 V8 W1 W2 W3 W4 W5 W6 W7 W8 X1 X2 X3 X4 X5 X6 X7 X8
FIN1 FIN3 FIN5 FIN9 FIN10 FIN14 FIN18 FIN22 VDD FIN0 VSS FIN8 VDD33 FIN13 VSS FIN21 CP15_0 CP15_1 CP15_2 CP15_3 CP15_4 CP15_5 CP15_6 FIN20
V9 V10 V11 V12 V13 V14 V15 V16 W9 W10 W11 W12 W13 W14 W15 W16 X9 X10 X11 X12 X13 X14 X15 X16
FIN23 FIN26 FIN31 FRXCTL2 FRXCTL5 NC9 JTDO NC11 VDD FIN29 VSS FRXCTL1 VDD FRXCLK VSS FTXCLK FIN25 FIN28 FIN30 FRXCTL3 FRXCTL4 FRXCTL6 JTRSTX FTXCTL6
V17 V18 V19 V20 V21 V22 V23 V24
W 1-29
FTXCTL5 FTXCTL2 FOUT31 FOUT26 FOUT23 FOUT22 FOUT18 FOUT14 VDD33 FTXCTL1 VSS FOUT29 VDD FOUT21 VSS FOUT13 FTXCTL4 FTXCTL3 FOUT30 FOUT28 FOUT25 FOUT20 CP14_6 CP14_5
V25 V26 V27 V28 V29
FOUT10 FOUT9 FOUT5 FOUT3 FOUT1
Freescale Semiconductor, Inc...
W17 W18 W19 W20 W21 W22 W23 W24
X 1-29
W25 W26 W27 W28 W29
VDD FOUT8 VSS FOUT0 VDD33
X17 X18 X19 X20 X21 X22 X23 X24
X25 X26 X27 X28 X29
CP14_4 CP14_3 CP14_2 CP14_1 CP14_0
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CHAPTER 2: SIGNAL DESCRIPTIONS
Table 30 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN FUNCTION PIN Y 1-29 FUNCTION PIN FUNCTION
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Z1 Z2 Z3 Z4 Z5 Z6 Z7 Z8 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8
VSS CP13_0 VDD CP13_1 VSS CP13_2 VDD33 CP13_3 CP9_0 CP9_1 CP9_2 CP9_3 CP9_4 CP9_5 CP9_6 CP11_0 VDD CP7_0 VSS CP7_1 VDD CP7_2 VSS CP7_3
Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Z9 Z10 Z11 Z12 Z13 Z14 Z15 Z16 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16
VSS CP13_4 VDD CP13_5 VSS CP13_6 VDD CP12_6 CP11_1 CP11_2 CP11_3 CP11_4 CP11_5 CP11_6 JTMS CP10_6 VDD33 CP7_4 VSS CP7_5 VDD CP7_6 VSS CP6_6
Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24
Z 1-29
VSS CP12_5 VDD33 CP12_4 VSS CP12_3 VDD CP12_2 CP10_5 CP10_4 CP10_3 CP10_2 CP10_1 CP10_0 CP8_6 CP8_5 VDD CP6_5 VSS CP6_4 VDD33 CP6_3 VSS CP6_2
Y25 Y26 Y27 Y28 Y29
VSS CP12_1 VDD CP12_0 VSS
Freescale Semiconductor, Inc...
Z17 Z18 Z19 Z20 Z21 Z22 Z23 Z24
AA 1-29
Z25 Z26 Z27 Z28 Z29
CP8_4 CP8_3 CP8_2 CP8_1 CP8_0
AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24
AA25 AA26 AA27 AA28 AA29
VDD CP6_1 VSS CP6_0 VDD
C5NP
JTAG Support
63
Table 30 Signals Listed by Pin Number (continued)
PIN FUNCTION PIN FUNCTION PIN AB 1-29 FUNCTION PIN FUNCTION
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8
CP3_0 CP3_1 CP3_2 CP3_3 CP3_4 CP3_5 CP3_6 CP5_0 VSS CP1_0 VDD CP1_1 VSS CP1_2 VDD CP1_3
AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16
CP5_1 CP5_2 CP5_3 CP5_4 CP5_5 CP5_6 JTDI CP4_6 VSS CP1_4 VDD33 CP1_5 VSS CP1_6 VDD CP0_6
AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24
AC 1-29
CP4_5 CP4_4 CP4_3 CP4_2 CP4_1 CP4_0 CP2_6 CP2_5 VSS CP0_5 VDD CP0_4 VSS CP0_3 VDD33 CP0_2
AB25 AB26 AB27 AB28 AB29
CP2_4 CP2_3 CP2_2 CP2_1 CP2_0
Freescale Semiconductor, Inc...
AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24
AC25 AC26 AC27 AC28 AC29
VSS CP0_1 VDD CP0_0 VSS
JTAG Support
The C-5 NP contains JTAG test logic compliant with the IEEE 1149.1 specification. All required public instructions are implemented, as well as some optional instructions. This section contains information regarding the pinout, instructions, identification codes, and boundary scan cell types.
Pinout
The C-5 NP uses the standard JTAG pins including the optional test reset pin. Table 28 describes the pins and their functions. Note that pins for JTRSTX, JTDI, and JTMS require external pullups on the board. These ports do not have internal pullups as required by the 1149.1 specification.
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CHAPTER 2: SIGNAL DESCRIPTIONS
JTAG Data Registers
The C-5 NP contains the standard internal registers as specified in IEEE 1149.1. These registers are described in Table 31.
Table 31 JTAG Internal Register Descriptions
REGISTER NAME REGISTER LENGTH DESCRIPTION
Bypass
1 1807 32
Standard JTAG bypass register Boundary Scan Register Standard JTAG IDCODE Register
Freescale Semiconductor, Inc...
Boundary Device Identification
Boundary Scan Cell Types
The C-5 NP boundary scan register contains only two cell types. All input cells are observe only cells of type BC_4. All enable and output cells are standard cells of type BC_1. In IEEE 1149.1-1990 specification, the BC_4 cell is shown in Figure 7 and the BC_1 cell is shown in Figure 8.
Figure 7 Observe-Only Cell
To next cell To System Logic G1 0 1 Shift DR From last cell Clock DR
From System Pin
1D C1
C5NP
JTAG Support
65
Figure 8 Cell Design That Can Be Used for Both Input and Output Pins
Node To next cell G1 0 1 G1 0 1 From last cell Clock DR To System Logic
Shift DR From System Pin
Freescale Semiconductor, Inc...
1D C1
1D C1 Update DR
IDcode Register
The C-5 NP implements a standard 32bit JTAG identification register. Table 32 lists the value of the code for full identification and its sub-components.
Table 32 JTAG Identification Code and Its Sub-components
FIELD NAME WIDTH BIT POSITIONS BINARY VALUE
Version Part Number Manufacturer Identity LSB
4 16 11 1
31-28 27-12 11-1 0
0000 0000_0000_0000_0010 001_1001_0110 1
The concatenated 32bit value is hexidecimal 0000232d.
JTAG Instruction Register
The C-5 NP contains a 4bit instruction register. Table 33 lists the instructions that are supported.
Table 33 Instruction Register Instructions
INSTRUCTION MNEMONIC SELECTED REGISTER INSTRUCTION OPCODE
Extest Idcode
Boundary Scan Identification Register
0000 0001
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CHAPTER 2: SIGNAL DESCRIPTIONS
Table 33 Instruction Register Instructions (continued) (continued)
INSTRUCTION MNEMONIC SELECTED REGISTER INSTRUCTION OPCODE
Sample/Preload Highz Clamp Bypass Reserved* Reserved* Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass
*
Boundary Scan Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register Bypass Register
0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Freescale Semiconductor, Inc...
There are two reserved instructions intended for C-Port Corporation's internal use. These should not be programmed by users.
Boundary Scan Description Language
In order to simplify board test, C-Port Corporation has provided a boundary scan description language (BSDL) file in the C-Port web site support area that describes the complete set of instructions, boundary scan order, and identification code value in an industry standard format. This information can be found at: http://e-www.motorola.com/webapp/sps/site/homepage.jsp?nodeId=03M0ylgx1Ks.
C5NP
C5NPD0-DS/D
Chapter 3
Rev 04
ELECTRICAL SPECIFICATIONS
Freescale Semiconductor, Inc...
Absolute Maximum Ratings
Table 34 lists the absolute maximum ratings for the C-5 network processor. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and do not imply that operation under any conditions other than those listed under "Recommended Operating Conditions" (Table 35) is possible. Exposure to conditions beyond Table 34 can:
* *
Reduce device reliability Result in premature device failure, even with no immediate sign of failure
Prolonged exposure to conditions at or near the absolute maximum ratings could also result in reduced useful life and reliability of the C-5 NP.
Table 34 C-5 Network Processor Absolute Maximum Ratings
PARAMETER MIN MAX UNIT
VDD33 Supply Voltage (3.3V input)* VDD Supply Voltage (1.8V input)* Voltage on any pin Static Discharge Voltage Storage Temperature Absolute Maximum Junction Temperature
*
-0.5 -0.5 -0.5 2000/500 -40 -40
+5 +2.8 VDD33 + 0.5 +125 +125
V V V V C C
Voltages are relative to Ground Not to exceed VDD + 2.5V
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CHAPTER 3: ELECTRICAL SPECIFICATIONS
Recommended Operating Conditions
The recommended operating conditions describe an environment the C-5 NP network processor is expected to encounter during normal operation. Table 35 delineates the recommended operating parameters for the C-5 NP.
Table 35 C-5 Network Processor Recommended Operating Conditions
PARAMETER MIN MAX UNIT
Freescale Semiconductor, Inc...
VDD33 Supply Voltage VDD Supply Voltage IDD33 - VDD33 Supply Current IDD - VDD Supply Current Tj Junction Temperature
*
3.135 1.7
3.465 1.9 1.5* 14*
V V A A C
-40
100
Peak values to be used by power supply designer.
DC Characteristics
The DC electrical characteristics define the input operating conditions for proper operation and the output responses to applied DC signals and switch characteristics over specified voltage and temperature ranges. The DC electrical characteristics are specified within the recommended operating conditions including operating temperature and power supply range as stated in this data sheet. Table 36 outlines the C-5 NP DC characteristics.
Table 36 C-5 Network Processor DC Characteristics
PARAMETER* MIN MAX UNIT NOTES
LVTTL Input High Voltage LVTTL Input Low Voltage LVTTL Output High Voltage LVTTL Output Low Voltage LVTTL Input Current LVPECL Input High Voltage LVPECL Input Low Voltage LVPECL Output High Voltage
2.0 -0.3 2.4
VDD33+.3 0.8 0.4
V V V V A V V V Load = 50ohm to VDD33 - 2V @IOH = -2mA @IOL = +2mA VIN = 0V or VDD33
-5 VDD33 -1.165 -0.3 VDD33 -1.025
+5 VDD33+.3V VDD33 -1.475 VDD33 -0.880
C5NP
Power Sequencing
69
Table 36 C-5 Network Processor DC Characteristics (continued) (continued)
PARAMETER* MIN MAX UNIT NOTES
LVPECL Output Low Voltage LVPECL Input Current CPREF
VDD33 -1.810 -5 VDD33 -1.38
VDD33 -1.620 +5 VDD33 -1.26
V A V
Load = 50ohm to VDD33 - 2V Single-ended LVPECL reference
Freescale Semiconductor, Inc...
*
All voltages are relative to Ground unless otherwise indicated.
Each control input pin has a capacitance associated with it. The capacitance at the control input is due to the package and the input circuitry connected to the pin. Capacitance is based on these conditions: TA = 25C; VDD33 = 3.3V; f = 1MHz. Table 37 provides capacitance data.
Table 37 C-5 Network Processor Capacitance Data
PARAMETER TYPICAL MAX UNIT
Input/Output Pins Input Pins Clock Pins
7 6 6
8 7 7
pF pF pF
Power Sequencing
The VDD rail must be kept within 2.5V of the VDD33 rail. However, this rule can be violated for periods up to one second, as is typical during power sequencing, as long as:
* *
The VDD is not clamped to ground or some other low voltage. The number of power cycling events averages to less than once per day over the lifetime of the product.
It is intended that the VDD and VDD33 rail be sequenced to their final value together for most applications. It is also required that SCLK, SCLKX, TCLKI, PCLK, MDCLK, FTXCLK, and FRXCLK be running or begin running during power sequencing to propagate reset inside the C-5 NP. Figure 9 indicates the relationship between the clocks and PRSTX. There is no requirement that the asserting and deasserting edges of PRSTX be synchronous to the clocks. Reset must be asserted within 100s of power initiation. Typically, reset is held low during power initiation.
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CHAPTER 3: ELECTRICAL SPECIFICATIONS
Figure 9 Bringup Clock Timing Diagram
VDD, VDD33
100ms
Freescale Semiconductor, Inc...
PRSTX
)(
1ms 100ms
TCLKI, PCLK, SCLK, SCLKX, DCLK, FTXCLK, FRXCLK
)(
Power and Thermal Characteristics
Table 38 provides the derived power and thermal characteristics for the production version (Revision D0) of the C-5 NP.
Table 38 C-5 Network Processor Power and Thermal Characteristics
PARAMETER MIN TYP MAX UNITS TEST CONDITIONS
Power Dissipation, PD
10.5 11.5 12.5 14.5
15.0 16.0 17.5 20.0
18.0 19.0 20.5 23.0 100
W
166MHz core clock (See Note 1) 180MHz core clock (See Note 1) 200MHz core clock (See Note 1) 233MHz core clock (See Note 1)
Maximum Junction Temperature, TJ Thermal Resistance, junction to case, JC Thermal Resistance, junction to ambient, JA Thermal Resistance, junction to printed circuit board, JB 0.24 1.87 4.8
oC oC/W oC/W oC/W
See Note 2 See Note 2 See Note 2
C5NP
Power and Thermal Characteristics
71
Table 38 C-5 Network Processor Power and Thermal Characteristics (continued)
PARAMETER MIN TYP MAX UNITS TEST CONDITIONS
Thermal Resistance, Junction through Board to Ambient, JBA
6.0
See Note 2
Freescale Semiconductor, Inc...
Effective Thermal Resistance, effective
1.43
oC/W
See Note 3
Notes for Table 38: 1 Estimated power dissipation (+/-10%) is derived from measurements on the C-5 NP Revision D00 under following conditions:
* * * * * *
BMU memory operating at 125MHz. TLU memory operating at 133MHz. VDD = 1.8V, VDD33 = 3.3V, TJ at approximately 50o C. "Minimum" PD based on idle condition (clocks running and no programs executing). "Typical" PD based on test application that implements Fast Ethernet forwarding actively running on all CPs. "Maximum" PD based on projected maximum consumption for any high-bandwidth communications application executing on all CPs, FP, and XP.
2 Thermal performance specifications based on following conditions:
*
Printed circuit board is based on the C-Ware Development System's C-5 NP Switch Module reference design, with specifications of: - 14 total layers (5 planes). Planes at least 100mm x 100mm below the C-5 NP before any interruptions. - FR4 board material, Cu signal and plane material. - 0.5mils signal layer thickness, 1.4mils plane layer thickness. - Thermal resistance, board to ambient (BA) of 1.2 oC/W.
*
Custom heat sink design has the following characteristics:
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CHAPTER 3: ELECTRICAL SPECIFICATIONS
- Dimensions: 100mm x 80mm x 10mm (height) - Thermal resistance heat sink to ambient (SA) of 1.6 oC/W @200 LFM. Figure 10 provides the characteristic thermal resistance curve for this heat sink for various airflow rates. - Thermal resistance case to heat sink (CS) of 0.03 oC/W (Chromerics T705 thermal material).
Freescale Semiconductor, Inc...
- Note that target heat sink design is for low profile (10mm height) applications. Significantly better thermal performance is possible with taller and/or wider designs. Contact your C-Port representative for heat sink options. 3 Effective Thermal Resistance (effective = JAJBA / (JA + JBA)) reflects the total thermal performance of the heat sink and board, as outlined in Note 2 above.
Figure 10 Thermal Performance for C-5 Network Processor Heat Sink (see step 2 above)
3
Thermal Resistance ( C/W)
2
1
0 0 200 400 600 800 1000
Velocity (ft/min)
Theoretical calculation of thermal resistance as a function of airflow velocity across heat sink
AC Timing Specifications
AC timing specifications consist of input requirements and output responses. The input requirements include setup and hold times, pulse widths, and high and low times. The output responses include delays from clock to signal. The AC timing specifications are defined separately for each interface to the C-5 NP Unless otherwise noted, all AC specifications were tested within the functional operating range.
C5NP
AC Timing Specifications
73
See Figure 11. Output timing specifications for LVTTL pins are given with a 10pF load on the output. Other loads can be simulated with the IBIS model available from C-Port. The LVPECL driver is specified into a 50 load terminated to a (VDD33 - 2V) reference.
Figure 11 Test Loading Conditions
LVTTL
Freescale Semiconductor, Inc...
DUT 10pF
VDD33
+2V
LVPECL DUT 50
Clock Timing Specifications
Cycle 1 SCLK SCLKX Tsc Tsh
The system clock timing is shown in Figure 12 and described in Table 39.
Figure 12 System Clock Timing Diagram
Cycle 2 Cycle 3 Cycle 4 Cycle 5
Tsl
CCLKn
TccN
Tcch
Tccl
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CHAPTER 3: ELECTRICAL SPECIFICATIONS
Table 39 System Clock Timing Description
MIN SYMBOL PARAMETER 1X CLK MODE 2X CLK MODE TYP MAX 1X CLK MODE 2X CLK MODE UNIT COMMENT
Tsc
System Cycle Time
Freescale Semiconductor, Inc...
6.0 5.0 4.3 45 45
3.0 2.5 2.14 30 30 647.67 488.28 29.097 22.353 20.00 9.412 8.00 6.43 55 55 70 70
ns
166MHz core clock 200MHz core clock 233MHz core clock Duty cycle* Duty cycle
Tsh Tsl Tcc0 Tcc1 Tcc2 Tcc3 Tcc4 Tcc5 Tcc6 Tcc7 Tcch Tccl
*
Sys Clk High Pulse Sys Clk Low Pulse CCLK0 Cycle Time CCLK1 Cycle Time CCLK2 Cycle Time CCLK3 Cycle Time CCLK4 Cycle Time CCLK5 Cycle Time CCLK6 Cycle Time CCLK7 Cycle Time CCLKm High Time CCLKm Low Time
ns ns ns ns ns ns ns ns 60% 60% 60% 60%
T1 E1 E3 T3 RMII Fibre Channel GMII OC-3 % cycle pulse is high % cycle pulse is low
40% 40%
40% 40%
Pulse duty cycle measured at crossing voltage of SCLK/SCLKX The frequencies specified for CCLK0 - CCLK7 allow full flexibility for the C-5 NP . Clock inputs associated with a specific protocol should be tied to ground when that protocol is not used by the C-5 NP . It is also possible to use one or more CCLKn inputs for other frequencies; contact your C-Port representative for more information.
Unused clocks should be pulled to a known state (ground) through a resistor. If you are using a clock generator, disabling the output should not cause a tristate. If it does, then the line should be pulled down.
CP Timing Specifications
This section describes the timing for the following CP interfaces:
* * * *
C5NP
DS1/DS3 Ethernet Timing Description 10/100 Ethernet Timing Description Gigabit GMII/MII Ethernet Interface Timing Description OC-3 Timing Description
AC Timing Specifications
75
* *
Gigabit TBI Interface Timing Description OC-12 Timing Description
DS1/DS3 Timing Specifications The DS1/DS3 interface timing is shown in Figure 13 and described in Table 40.
Freescale Semiconductor, Inc...
Figure 13 DS1/DS3 Ethernet Timing Diagram
Cycle 1 CPn_0 (TCLK) Tcdt CPn_2/3 (Tx) Cycle 2 Cycle 3 Cycle 4 Cycle 5
Tcdo
Cycle 2 CPn_1 (RCLK) Cycle 3 Cycle 4 Cycle 5
Tcdr
CPn_4/5 (Rx)
Tcds
Tcdh
Table 40 DS1/DS3 Ethernet Timing Description
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
Tcdt
Tcdo
Tcdr
Tcds
Tcdh
DS1/DS3 Transmit Cycle Time
DS1/DS3 Output Time
DS1/DS3 Receive Cycle Time
DS1/DS3 Setup Time
DS1/DS3 Hold Time
647/22.4
3.0/3.0
647/22.4
2.0
2.5
ns
400/15.0
ns
ns
ns
ns
10/100 Ethernet Timing Specifications The 10/100 Ethernet interface timing is shown in Figure 14 and described in Table 41.
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CHAPTER 3: ELECTRICAL SPECIFICATIONS
Figure 14 10/100 Ethernet Timing Diagram
Cycle 1 CPn_0 (TCLK) Tcet CPn_2/3/6 (Tx) Cycle 2 Cycle 3 Cycle 4 Cycle 5
Freescale Semiconductor, Inc...
Tceo
CPn_1/4/5 (Rx)
Tces
Tceh
Table 41 10/100 Ethernet Timing Description
SYMBOL PARAMETER MIN TYP MAX UNIT
Tcet Tceo Tces Tceh
*
Transmit Cycle Time* Output Time Setup Time Hold Time 3.0 2.0 2.5
20 15.0
ns ns ns ns
STD/Fast Ethernet
Gigabit GMII Ethernet, TBI and MII Interface Timing Specifications The Gigabit GMII Ethernet interface timing is shown in Figure 15 and described in Table 42. The TBI interface timing is shown in Figure 15 and described in Table 43.
C5NP
AC Timing Specifications
77
Figure 15 Gigabit Ethernet and TBI Interface Timing Diagram
GMII / TBI Tx
CPn_0 (TCLK) Tcgt Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
CPn_2-6 (Tx) CPn+1_2-6 (Tx)
Freescale Semiconductor, Inc...
Tcgo
MII Tx
MII CPn_1 (TCLK)
Cycle 1
Cycle 2
Cycle 3
Tcmt MII CPn_2-6 (Tx)
Tcmo
TBI Rx
CPn+2_1 (RCLKN) CPn+3_1 (RCLK)
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Tctr
Tctd
CPn_2-6 (Rx) CPn+1_2-6 (Rx)
Tcts
Tcth
GMII Rx
CPn+2_1 (RCLK)
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
CPn+2_2-6 (Rx) CPn+3_2-6 (Rx)
Tcgr
Tcgs
Tcgh
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CHAPTER 3: ELECTRICAL SPECIFICATIONS
Table 42 Gigabit GMII/MII Ethernet Interface Timing Description
SYMBOL GIGABIT PARAMETER MIN TYP MAX UNIT COMMENT
Tcgt Tcgo Tcgr
Transmit Cycle Time, GMII Output Time, GMII Receive Cycle Time Setup Time Hold Time Transmit Cycle Time, MII Output Time, MII 2 1.5 0.5 3.0
8.0 6.0 8.0
ns ns ns ns ns
Freescale Semiconductor, Inc...
Tcgs Tcgh Tcmt Tcmo
40/400 12
ns ms
100BaseT/10BaseT
Table 43 Gigabit TBI Interface Timing Description
SYMBOL TBI PARAMETER MIN TYP MAX UNIT
Tctt Tcto Tctr Tctd Tcts Tcth
*
Transmit Cycle Time Output Time Receive Cycle Time Rclk/Rclkn Deviation Setup Time Hold Time 1.5 0.5 3.0
8.0 6.0* 16.0 1.0
ns ns ns ns ns ns
For Fibre Channel applications this value is 7.0ns for a transmit cycle time of 9.4ns.
OC-3 Timing Specifications The OC-3 interface timing is shown in Figure 16 and described in Table 44.
C5NP
AC Timing Specifications
79
Figure 16 OC-3 Timing Diagram
Cycle 1 CPn_2 Tc3t Cycle 2 Cycle 3 Cycle 4 Cycle 5
Freescale Semiconductor, Inc...
CPn_3 Tc3i Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
CPn_0 CPn_1 Tc3r Tc3d CPn_4 Tc3s CPn_5 Tc3s Tc3h Tc3h
Table 44 OC-3 Timing Description
SYMBOL PARAMETER MIN TYP MAX UNIT
Tc3t Tc3i Tc3r Tc3d Tc3s Tc3h
*
OC-3 Transmit Cycle Time OC-3 Pulse Width OC-3 Receive Cycle Time* OC-3 Clock Duty Cycle OC-3 Setup Time OC-3 Hold Time 2.0 6.0 40 2.0 2.5
6.43
ns ns ns 60 % ns ns
155.52MHz
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CHAPTER 3: ELECTRICAL SPECIFICATIONS
OC-12 Timing Specifications The OC-12 interface timing is shown in Figure 17 and described in Table 45.
Figure 17 OC-12 Timing Diagram
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
Freescale Semiconductor, Inc...
CPn_1 (TCLKI) Tc12i
Tc12d
CPn_0 (TCLK)
Tc12t
CPn_2-6 (Tx)
Tc12o
Cycle 1
Cycle 2
Cycle 3
CPn_1 (RCLK)
Tc12r
CPn_2-6 (Rx)
Tc12s Tc12h
Table 45 OC-12 Timing Description
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
Tc12i
Tc12d
Tc12t
Tc12o
Tc12r
Tc12s
Tc12h
*
OC-12 Transmit Cycle Time*
OC-3 Clock Duty Cycle
OC-12 Transmit Cycle Time
OC-12 Output Time
OC-12 Receive Cycle Time
OC-12 Setup Time
OC-12 Hold Time
12.86
40
12.86
3.0
12.0
2.0
2.5
ns
60
10.0
%
ns
ns
ns
ns
ns
12.86
Input from PHY Output from C-5 NP Aligned to TCLK
C5NP
AC Timing Specifications
81
Executive Processor Timing Specifications
The XP timing specifications include:
Freescale Semiconductor, Inc...
* * * *
PCI Timing Specifications MDIO Serial Interface Timing Specifications Low Speed Serial Interface Timing Specifications PROM Interface Timing Specifications
PCI Timing Specifications The PCI timing is shown in Figure 18 and described in Table 46.
Figure 18 PCI Timing Diagram
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
PCLK Tpc PAD/P_ctl (output)
Tpao
Tpaz
Tpav
PAD/P_ctl (input)
Tpas Tpah
PGNTX (input)
Tpgs Tpgh
PIDSEL (input)
Tpis Tpih
Table 46 PCI Timing Description
SYMBOL PARAMETER MIN TYP MAX UNIT
Tpc Tpas
PCI Cycle Time* PAD/P_ctl Setup
15.0 3.0
ns ns
V 04
82
CHAPTER 3: ELECTRICAL SPECIFICATIONS
Table 46 PCI Timing Description (continued) (continued)
SYMBOL PARAMETER MIN TYP MAX UNIT
Tpah Tpao Tpaz Tpav Tpgs Tpgh Tpis Tpih
PAD/P_ctl Hold PAD/P_ctl Output PAD/P_ctl Clk to Tri PAD/P_ctl Clk to Driven PGNTX Setup PGNTX Hold PIDSEL Setup PIDSEL Hold PRSTX** PINTA**
0.0 2.0 1.8 1.3 5.1 0.0 5.0 0.0 6.0 5.5 5.5
ns ns ns ns ns ns ns ns ns ns
Freescale Semiconductor, Inc...
*
66MHz PCI P_ctl includes all PCI control parameters including: PPAR, PFRAMEX, PTRDYX, PIRDYX, PSTOPX, PDEVSELX, PPERRX, PSERRX Not fully tested, values based on design/characterization. ** Asynchronous
MDIO Serial Interface Timing Specifications The MDIO serial interface timing is shown in Figure 19 and described in Table 47.
Figure 19 MDIO Serial Interface Timing Diagram
Cycle 2 Cycle 3 Cycle 4
SICL
Tsic
SIDA (output)
Tsods Tsodh
SIDA (input) Tsids
C5NP
AC Timing Specifications
83
Table 47 MDIO Serial Interface Timing Description
SYMBOL PARAMETER MIN TYP MAX UNIT
Tsic Tsids Tsidh Tsods Tsodh
SICL Cycle Time SIDA Input Setup SIDA Input Hold SIDA Output Setup SIDA Output Hold
40 10 0.0 10 10
ns ns ns ns ns
Freescale Semiconductor, Inc...
Low Speed Serial Interface Timing Specifications The low speed serial interface timing is shown in Figure 20 and described in Table 48.
Figure 20 Low Speed Serial Interface Timing Diagram
Cycle 2
Cycle 3
SICL
Tsu:s
SIDA
Thd:s
Thd:d
Tsu:d
Tcyc
Tsu:stop
Tbuf
Table 48 Low Speed Serial Interface Timing Description
SYMBOL
PARAMETER
MIN
MAX
UNIT
Tcycle
Tsu:s
Thd:s
Tsu:d
Thd:d
Tsu:stop
SICL Cycle Time
Set-up Time for Repeated START Condition
Hold Time START Condition
Data Set-up Time
Data Hold Time
Set-up Time for STOP Condition
2500
600
600
250
0.0
600
ns
ns
ns
ns
ns
ns
V 04
84
CHAPTER 3: ELECTRICAL SPECIFICATIONS
Table 48 Low Speed Serial Interface Timing Description (continued) (continued)
SYMBOL PARAMETER MIN MAX UNIT
Tbuf Cmax
Bus Free Time Between a STOP and START Condition Capacitive load for each line of the bus
1250 400
ns pF
Freescale Semiconductor, Inc...
PROM Interface Timing Specifications The PROM interface timing is shown in Figure 21 and described in Table 49.
Figure 21 PROM Interface Timing Diagram
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
SPCK Tspc SPDI
Tspis Tspih
SPLD
Tsplo
SPDO
Tspdo
Table 49 PROM Interface Timing Description
SYMBOL
PARAMETER
CLOCK MODE
MIN
TYP
MAX
UNIT
Tspc
Tspis
Tspih
Tsplo
Tspdo
*
SPCK Cycle Time
SPDI Setup
SPDI Hold
SPLD Output
SPDO Output
40.0
10.0
0.0
1X
2X
1X
2X
ns
ns
ns
Tsc + 3.0
2 x Tsc + 3.0
Tsc + 3.0
2 x Tsc + 3.0
Tsc*
2 x Tsc*
Tsc*
2 x Tsc*
ns
ns
ns
ns
Tsc is the System Cycle Time. See Table 39 on page 74
C5NP
AC Timing Specifications
85
Fabric Processor Timing Specifications
Cycle 1
The FP timing specifications are shown in Figure 22 and described in Table 50.
Figure 22 Fabric Processor Timing Diagram
Cycle 2 Cycle 3 Cycle 4 Cycle 5
FRXCLK
Freescale Semiconductor, Inc...
Tfrc FRXCTL (output) Tfrco FRXCTL (input) Tfrcs FINn Tfrds Tfrdh Tfrch Tfrcz Tfrcv
FTXCLK Tftc FTXCTL (output) Tftco FTXCTL (input) Tftcs FOUTn Tftdo Tftch Tftcz Tftcv
Table 50 Fabric Processor Timing Description
SYMBOL PARAMETER MIN TYP MAX UNIT COMMENT
Tfrc Tfrcs Tfrch
FRX Cycle Time FRXCTL Setup FRXCTL Hold
9.0 4.0 1.5 0.5
ns ns ns Utopia2 Mode All other modes
V 04
86
CHAPTER 3: ELECTRICAL SPECIFICATIONS
Table 50 Fabric Processor Timing Description (continued)
SYMBOL PARAMETER MIN TYP MAX UNIT COMMENT
Tfrco Tfrcz Tfrcv Tfrds Tfrdh Tftc Tftcs Tftch Tftco Tftcz Tftcv Tftdo
*
FRXCTL Output FRXCTL Clk to Tri* FRXCTL Clk to Driven* FIN Setup FIN Hold FTX Cycle Time FTXCTL Setup FTXCTL Hold FTXCTL Output FTXCTL Clk to Tri* FTXCTL Tri to Driven* FOUT Output
1.0 1.8 1.3 4.0 1.5 0.5 9.0 4.0 1.5 0.5 1.0 1.7 1.3 1.0
3.4 5.5 5.5
ns ns ns ns ns ns ns ns Utopia2 Mode All other modes Utopia2 Mode All other modes
Freescale Semiconductor, Inc...
3.6 5.5 5.5 3.6
ns ns ns ns
Not fully tested, values based on design/characterization.
BMU Timing Specifications
The BMU timing specifications are shown in Figure 23 and described in Table 51. The BMU synchronous DRAM interface is PC100-compliant and designed to work with industry standard SDRAM components with 12 or fewer address lines. The information below is intended to provide the output, setup, and hold data required to design this interface without duplicating the transaction waveform diagrams in SDRAM data sheets.
C5NP
AC Timing Specifications
87
Figure 23 BMU Timing Diagram
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
MDCLK Tmc
Freescale Semiconductor, Inc...
M_ctl
Tmco
MAn
Tmao
MDn (output)
Tmdo
Tmdz
Tmdv
MDn (input)
Tmds
Tmdh
Table 51 BMU Timing Description
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
Tmc
Tmco
Tmao
Tmds
Tmdh
Tmdo
Tmdz
Tmdv
*
BMU Cycle Time
BMU Ctrl Output
BMU Addr Output
BMU Data Setup
BMU Data Hold
BMU Data Output
BMU Data Clk to Tri*
BMU Data Clk to Driven*
8.0
1.2
1.2
0.5
1.0
1.2
1.8
1.4
ns
3.7
3.8
ns
ns
ns
ns
4.0
4.0
4.0
ns
ns
ns
Not fully tested, values based on design/characterization.
Table 52 Signal Groups in BMU Timing Diagrams
SIGNAL GROUP
INCLUDED SIGNALS
Control (M_ctl)
Address (MAn)
Data (MDn)
MBA0, MBA1, MCASX, MRASX, MWEX, MCSX, MDQM
MA0 - MA11
MD0 - MD129, MDECC0 - MDECC8
V 04
88
CHAPTER 3: ELECTRICAL SPECIFICATIONS
TLU Timing Specifications
The TLU timing specifications are shown in Figure 24 and described in Table 53.
Figure 24 TLU Timing Diagram
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
TCLKI
Freescale Semiconductor, Inc...
Ttc T_ctl
Ttco
TAn
Ttao
TDn (output)
Ttdo
Ttdz
Ttdv
TDn (input)
Ttds
Ttdh
Table 53 TLU Timing Description
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
Ttc
Ttco
Ttao
Ttds
Ttdh
Ttdo
Ttdz
Ttdv
*
TLU Cycle Time
TLU Ctrl Output
TLU Addr Output
TLU Data Setup
TLU Data Hold
TLU Data Output
TLU Data Clk to Tri*
TLU Data Clk to Driven*
7.5
1.2
1.2
0.5
1.0
1.2
2.0
1.5
ns
3.4
3.4
ns
ns
ns
ns
3.5
3.5
3.5
ns
ns
ns
Not fully tested, values based on design/characterization.
Table 54 Signal Groups in TLU Timing Diagrams
SIGNAL GROUP
INCLUDED SIGNALS
Control (T_ctl)
Address (TAn)
TA18X - TA21X, TCE0X - TCE3X, TWE0X - TWE3X
TA0 - TA21
C5NP
AC Timing Specifications
89
Table 54 Signal Groups in TLU Timing Diagrams
SIGNAL GROUP INCLUDED SIGNALS
Data (TDn)
TD0 - TD63
QMU Timing Specifications
The QMU timing specifications are shown in Figure 25 and described in Table 55.
Figure 25 QMU Timing Diagram
Freescale Semiconductor, Inc...
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
QCLK Tqc QCMDn (output) Tqco QDATAn (output) Tqdo QDATAn (input) Tqds Tqdh Tqdz Tqdv
Table 55 QMU Timing Description
SYMBOL PARAMETER MIN TYP MAX UNIT COMMENT
Tqc Tqco Tqds Tqdh Tqdo Tqdz
QMU Cycle Time QMU Ctrl Output QMU Data Setup QMU Data Hold QMU Data Output QMU Data Clk to Tri*
2 x Tsc 4 x Tsc 1.5 3.1 1.3 1.5 1.1 3.5 1/2 Tsc + 1.0 Tsc + 1.0 5.5 1/2 Tsc + 1.0 Tsc + 1.0
ns ns ns ns ns ns ns
1X Clock Mode 2X Clock Mode 1X Clock Mode 2X Clock Mode
1X Clock Mode 2X Clock Mode
V 04
90
CHAPTER 3: ELECTRICAL SPECIFICATIONS
Table 55 QMU Timing Description (continued) (continued)
SYMBOL PARAMETER MIN TYP MAX UNIT COMMENT
Tqdv
*
QMU Data Clk to Driven* 0.6
5.5
ns
Not fully tested, values based on design/characterization.
Freescale Semiconductor, Inc...
Table 56 Signal Groups in QMU Timing Diagrams
SIGNAL GROUP INCLUDED SIGNALS
QCMDn QDATAn
QCMD0 - QCMD15, QSFLOW, QXCTRL0, QXCTRL1, QXRQST QDATA0 - QDATA31, QDPAR
C5NP
C5NPD0-DS/D
Chapter 4
Rev 04
MECHANICAL SPECIFICATIONS
Freescale Semiconductor, Inc...
Package Views
The C-5 network processor is an 838 pin (29 pins x 29 pins) Ball Grid Array (BGA) package as shown in the following illustrations. Table 57 defines the package measurements.
Figure 26 C-5 Network Processor BGA Package Side View
A4
A2 A3
A A1
Seating Plane
HiTCE: Green ceramic is thermally matched to FR4 circuit board. The aluminum lid is electrically connected to the grounded substrate of the C-5 NP. Neither the lid nor any heat sink connected to the lid should be part of a current-carrying path. It is acceptable, however, to connect the lid or heatsink to ground if necessary (through the standoff screws for the heat sink).
V 04
94
CHAPTER 4: MECHANICAL SPECIFICATIONS
Figure 27 C-5 Network Processor BGA Package (Bottom View)
D D1 e
AC AB AA Z Y X W V U T S R Q P O N M L K J I H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Freescale Semiconductor, Inc...
e
E1
E
b
Package Measurements
Table 57 defines the C-5 NP package measurements, providing nominal, minimum, and maximum sizes where appropriate.
C5NP
Marking Codes
95
Table 57 Package Measurements (Reference Figure 26 and Figure 27 for Symbols)
SYMBOL DEFINITION NOM. (MM) MIN. (MM) MAX. (MM)
A A1 A2 A3 A4 D D1 E E1 e b
Overall Ball height C4 and Die Body thickness Lid thickness Body size Ball footprint (X) Body size Ball footprint (Y) Ball pitch Ball diameter
5.63 0.89 0.88 2.26 1.6 37.50 35.56 37.50 35.56 1.27 0.89
5.31
5.95
Freescale Semiconductor, Inc...
2.07
2.53
Marking Codes
Table 58 explains the marking on the C-5 NP.
Table 58 C-5 Network Processor Marking Codes
MARKING (EXPLANATION OF CODES)
Top Bottom Pin 1 Marking
Logo/Part#/Country of Origin/Date Code N/A Chamfered Corner
Reflow
Typical Reflow Profile for the C-5 Switch Module 1 Follow the guidelines recommended by your solder paste supplier. Flux requrements must be met for best solderability. 2 The temperature profile should be carefully characterized to ensure uniform temperature across the board and package. Solder ball voiding may be affected by ramp rates and dwell times below and above liquidus.
V 04
96
CHAPTER 4: MECHANICAL SPECIFICATIONS
3 A nitrogen atmosphere is not required, but will make the process more robust. It can make a difference for marginally solderable PC board pads. 4 Full convection forced air furnaces work best, but IR, Convection/IR, or vapor phase can be used.
Freescale Semiconductor, Inc...
C5NP
C5NPD0-DS/D Rev 04
INDEX
Freescale Semiconductor, Inc...
Symbols
10/100 Ethernet (RMII) Configuration 32 10/100 Ethernet Signals 32 10/100 Ethernet Timing Description 77 10/100 Ethernet Timing Diagram 77 10/100 Ethernet Timing Specifications 76
A
About This Guide 13 Absolute Maximum Ratings 67 AC Timing Specifications 72
B
Block Diagram, C-5 Network Processor 21 BMU SDRAM Interface Signals 47 BMU Signal Groups 89 BMU Timing Description 89 BMU Timing Diagram 89 BMU Timing Specifications 88 Boundary Scan Cell Types 63 Boundary Scan Description Language 66 Bringup Clock Timing Diagram 70 Buffer Management Unit 24
Channel Processor Interface Signals 30 Channel Processors 22 Channel Processors Physical Interface Signals and Pins Grouped by Clusters 31 Clock and Reference Signals 29 Clock Signals 29 Clock Timing Specifications 73 Configuration 10/100 Ethernet (RMII) 32 DS1/T1 Framer Interface 32 FibreChannel TBI 35 Gigabit Ethernet 35 Gigabit Ethernet (GMII) 33 SONET OC-12 Transceiver Interface 37 SONET OC-3 Transceiver Interface 37 Configurations GMII/TBI Transmit and Receive Pin 34 Connections Power and Ground (Bottom View) 52 CP Timing Specifications 75
D
Data Registers JTAG 63 Data Sheet Description and Organization 13 DC Characteristics 68 Description Functional 19 Description Language Boundary Scan 66 Descriptions Signal 27 Diagram 10/100 Ethernet Timing 77 BMU Timing 89 V 04
C
C-5 Network Processor Absolute Maximum Ratings 67 C-5 Network Processor BGA Package, Bottom View 94 C-5 Network Processor BGA Package, Side View 93 C-5 Network Processor Capacitance Data 69 C-5 Network Processor DC Characteristics 68 C-5 Network Processor Power and Thermal Characteristics 70 C-5 NP Channel Processors 22
98
INDEX
Freescale Semiconductor, Inc...
Bringup Clock Timing 70 DS1/DS3 Ethernet Timing 76 Fabric Processor Timing 87 Gigabit Ethernet (TBI) Timing 78 Low Speed Serial Interface Timing 85 MDIO Serial Interface Timing 84 OC-3 Timing 80 PCI Timing 82 Pinout 27 PROM Interface 42 PROM Interface Timing 86 QMU Timing 91 Signal Groups in BMU Timing 89 Signal Groups in QMU Timing 92 Signal Groups in TLU Timing 90 System Clock Timing 74 TLU Timing 90 Diagram, Block C-5 Network Processor 21 DS1/DS3 Ethernet Timing Description 76 DS1/DS3 Ethernet Timing Diagram 76 DS1/DS3 Timing Specifications 75 DS1/T1 Framer Interface Configuration 32 DS1/T1 Framer Interface Signals 32
Fabric Processor 24 Fabric Processor Interface Signals 44 Fabric Processor Timing Description 87 Fabric Processor Timing Diagram 87 Fabric Processor Timing Specifications 86 Functional Description 19
G
General System Interface Signal 43 Gigabit Ethernet (GMII) Configuration 33 Gigabit Ethernet (GMII) Signals One Cluster Example 34 Gigabit Ethernet (TBI) Timing Description 79, 79 Gigabit Ethernet (TBI) Timing Diagram 78 Gigabit Ethernet and FibreChannel TBI Configuration 35 Gigabit Ethernet and FibreChannel TBI Signals Example 36 Gigabit GMII Ethernet, TBI and MII Interface Timing Specification 77 GMII/TBI Transmit and Receive Pin Configurations 34 Guide Conventions 14
I
IDcode Register 64 Instruction Register Instructions 65
E
Electrical Specifications 67 Absolute Maximum Ratings 67 Executive Processor 22 PCI 23 PROM Interface 23 Serial Bus Interface 23 System Interface Signals 39 System Interfaces 23 Executive Processor Timing Specifications 82
J
JTAG Data Registers 63 JTAG Identification Code and Its Sub-components 65 JTAG Instruction Register 65 JTAG Internal Register Descriptions 63 JTAG Support Pinouts 63
F
Fabric Interface Pin Mapping Power X Mode 47 PRIZMA Mode 46 Utopia2/Utopia3 ATM Mode 45 Utopia2/Utopia3 PHY Mode 45
L
Low Speed Serial Interface Timing Description 85 Low Speed Serial Interface Timing Diagram 85 Low Speed Serial Interface Timing Specifications 84 LVPECL Specifications 29 LVTTL Specifications 29
C5NP
INDEX
99
M
MDIO Serial Interface Timing Description 84 MDIO Serial Interface Timing Diagram 84 MDIO Serial Interface Timing Specifications 83 Measurements C-5 Network Processor 94 Mechanical Specifications 93 Miscellaneous Test Signals for JTAG, Scan, and Internal Test Routines 53
Processor, Fabric 24 PROM Interface Diagram 42 PROM Interface Signals 41 PROM Interface Timing Description 86 PROM Interface Timing Diagram 86 PROM Interface Timing Outline 43 PROM Interface Timing Specifications 85
Freescale Semiconductor, Inc...
Q
QMU Signal Groups 92 QMU SRAM Interface Signals 50 QMU Timing Description 91 QMU Timing Diagram 91 QMU Timing Specifications 91 Queue Management Unit 25
N
No Connection Pins 53
O
OC-12 Signals 38 OC-12 Timing Description 81 OC-12 Timing Specifications 81 OC-3 Signals 37 OC-3 Timing Description 80 OC-3 Timing Diagram 80 OC-3 Timing Specifications 79 Operating Conditions, Recommended 67
R
Recommended Operating Conditions 67 Register IDcode 64 JTAG Instruction 65 Related Product Documentation 17 revision history, for this guide 15
P
Package Measurements 94 PCI Signals 39 PCI Timing Description 83 PCI Timing Diagram 82 PCI Timing Specifications 82 Pin Descriptions Grouped by Function 28 Pin Locations 28 Pin Number Signals Groups 53 Pinout Diagram 27 Power and Ground Connections (Bottom View) 52 Power Sequencing 69, 70 Power Supply Signals 50 Power X Mode, Fabric Interface Pin Mapping 47 PRIZMA Mode, C-5 Network Processor to Fabric Interface Pin Mapping 46 Processor, Executive 22
S
Serial Interface Signals 40 Serial Port Signals 41 Signal General System Interface 43 Signal Descriptions 27 Signal Summary 27 Signals 10/100 Ethernet 32 BMU SDRAM Interface 47 Channel Processor Interface 30 Clock 29 Clock and Reference 29 DS1/T1 Framer Interface 32 Fabric Processor Interface 44 Grouped by Pin Number 53 OC-12 38 OC-3 37 V 04
100
INDEX
Freescale Semiconductor, Inc...
PCI 39 Power Supply 50 PROM Interface 41 QMU SRAM Interface 50 Serial Interface 40 Serial Port 41 Test 52 TLU SRAM Interface 49 SONET OC-12 Transceiver Interface Configuration 37 SONET OC-3 Transceiver Interface Configuration 37 Specifications 10/100 Ethernet Timing 76 AC Timing 72 BMU Timing 88 Clock Timing 73 CP Timing 75 DS1/DS3 Timing 75 Electrical 67 Executive Processor Timing 82 Fabric Processor Timing 86 Gigabit GMII Ethernet, TBI and MII Interface Timing Specification 77 Low Speed Serial Interface Timing 84 MDIO Serial Interface Timing 83 Mechanical 93 OC-12 Timing 81 OC-3 Timing 79 PCI Timing 82 PROM Interface Timing 85 QMU Timing 91 TLU Timing 90 XP Timing 82 System Clock Timing Description 74 System Clock Timing Diagram 74 System Interfaces
Executive Processor 23
T
Table Lookup Unit 25 Test Signals 52 Test Signals, Miscellaneous, For JTAG, Scan, and Internal Test Routines 53 Thermal Performance for C-5 Network Processor Heat Sink 72 Timing Outline PROM Interface 43 TLU Signal Groups 90 TLU SRAM Interface Signals 49 TLU Timing Description 90 TLU Timing Diagram 90 TLU Timing Specifications 90 Transceiver Interface Configuration SONET OC-12 37 SONET OC-3 37 Transmit and Receive Pin Combinations for Gigabit Ethernet and FibreChannel 33
U
Using C-Port Electronic Documents 13 Utopia2/Utopia3 ATM Mode, C-5 Network Processor to Fabric Interface Pin Mapping 45 Utopia2/Utopia3 PHY Mode, C-5 Network Processor to Fabric Interface Pin Mapping 45
X
XP Timing Specifications 82
C5NP
Freescale Semiconductor, Inc...
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